I2C "SCL" line problem

Hi all,

I faced the following problem with my I2C slave code(VHDL).

I was incrementing a counter on the negative edge of SCL(this clock is
coming from the processor's I2C port , 100 KHz frequency).
But what i observed on the CRO was that my bit counter which was
running on the "negative edge" of SCL , was incrementing on "positive
edge" also and this was not happening always.

The solution to this problem was i inverted the incomimg clock "SCL"
and used the rising edge to increment my counter now it was fine.

Can any I2C experts clarify what is the problem with working on
"negative edge of "SCL" clock.


Regards,
Prav

 

[woko]

Hi Praveen,

I would say that you disturbance on your SCL falling edge. If your
device see a short falling peak on the rising edge it could be falsely
interpreted as falling edge. See for the xilinx article "Two Simple
Solutions for Tricky Problems", solution "B" could help you.

Its interesting that you have trouble on I2C with the falling edge.
Because the devices pull to low level and let it float to high, I
thought you should have trouble on the rising edge.

cheers,

Wolfgang Kopp