J
junk_no_spam
Guest
Maybe not the correct place to ask this question, but I did see some I2C
threads here. Perhaps someone could direct me to a better format for
this question:
Philips I2C 2.1 spec suggests that full-speed(400KHz) and
high-speed(3.4MHz) devices can exist on the same I2C bus.
So for HS-mode (=3.4MHz device), the clk high/low period is
around ~150nsec.
And, the FS-mode (=400KHz device) has 50nsec glitch rejection filters
on SCL and SDA.
Then how does the FS-mode device reject the HS-mode traffic if the
anti-glitch filter on the FS-mode device passes all of the HS-mode
signaling???
I kind of assumed the anti-glitch filtering on the SCL/SDA
inputs to the FS-mode, would protect the FS-mode device from
HS-mode signals.
Do I need to do some additional digital filtering on the SCL/SDA inputs
to the FS-mode I2C blk in the FS-mode device? And this would be kinda
hard for an asynchronous(no master clk) I2C interface.
What did I miss in the Philips spec?
thanks,
-steve
threads here. Perhaps someone could direct me to a better format for
this question:
Philips I2C 2.1 spec suggests that full-speed(400KHz) and
high-speed(3.4MHz) devices can exist on the same I2C bus.
So for HS-mode (=3.4MHz device), the clk high/low period is
around ~150nsec.
And, the FS-mode (=400KHz device) has 50nsec glitch rejection filters
on SCL and SDA.
Then how does the FS-mode device reject the HS-mode traffic if the
anti-glitch filter on the FS-mode device passes all of the HS-mode
signaling???
I kind of assumed the anti-glitch filtering on the SCL/SDA
inputs to the FS-mode, would protect the FS-mode device from
HS-mode signals.
Do I need to do some additional digital filtering on the SCL/SDA inputs
to the FS-mode I2C blk in the FS-mode device? And this would be kinda
hard for an asynchronous(no master clk) I2C interface.
What did I miss in the Philips spec?
thanks,
-steve