I2C hangup

[Richard Henry]

I have noticed while checking out a prototype board that the I2C devices
occasionally hang the bus (SDA held low) preventing any further bus
transactions. My only fix is to cycle power to the board. That leads me to
wonder whether adding a fet power switch feeding the I2C devices controlled
by the micro might be of benefit - when the micro detects a hung bus, it can
"reset" the I2C devices.

Anyone ever have to do this?

 

[Joel Kolstad]

"Richard Henry" <rphenry@home.com> wrote in message
news:3iiq6fFlp5huU1@individual.net...

I have noticed while checking out a prototype board that the I2C devices
occasionally hang the bus (SDA held low) preventing any further bus
transactions.

Anyone ever have to do this?

Not personally, but you'll find some application notes on Phillip's web site
where they discuss the problem and propose various solutions. They make "bus
splitter" ICs that can be used to isolate "hung" portions of the bus, generate
error signals that can be used to reset processors, etc.

Part of the trick, though, is deciding how long SDA should be able to camp low
before you decide the bus is hung. I've heard of people sometimes using SDA
as a form of handshaking and allowing up to ten seconds before they time out
the bus!

---Joel

 

[John Larkin]

On Thu, 30 Jun 2005 10:58:35 -0700, "Richard Henry" <rphenry@home.com>
wrote:

I have noticed while checking out a prototype board that the I2C devices
occasionally hang the bus (SDA held low) preventing any further bus
transactions. My only fix is to cycle power to the board. That leads me to
wonder whether adding a fet power switch feeding the I2C devices controlled
by the micro might be of benefit - when the micro detects a hung bus, it can
"reset" the I2C devices.

Anyone ever have to do this?

Not me; I always use SPI.

John

 

[martin griffith]

On Thu, 30 Jun 2005 12:11:55 -0700, in sci.electronics.design John
Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Thu, 30 Jun 2005 10:58:35 -0700, "Richard Henry" <rphenry@home.com
wrote:

I have noticed while checking out a prototype board that the I2C devices
occasionally hang the bus (SDA held low) preventing any further bus
transactions. My only fix is to cycle power to the board. That leads me to
wonder whether adding a fet power switch feeding the I2C devices controlled
by the micro might be of benefit - when the micro detects a hung bus, it can
"reset" the I2C devices.

Anyone ever have to do this?


Not me; I always use SPI.

John

At last, a friend.........................................


martin

 

[Piotr Piatek]

On Thu, 30 Jun 2005 10:58:35 -0700, "Richard Henry" wrote:

I have noticed while checking out a prototype board that the I2C devices
occasionally hang the bus (SDA held low) preventing any further bus
transactions. My only fix is to cycle power to the board. That leads me to
wonder whether adding a fet power switch feeding the I2C devices controlled
by the micro might be of benefit - when the micro detects a hung bus, it can
"reset" the I2C devices.

Anyone ever have to do this?

Following solution is recommended by Atmel in the AT24C01 memory
datasheet:

MEMORY RESET: After an interruption in protocol, power loss or system
reset, any 2-wire part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.

Perhaps this would help.

Best regards

Piotr

 

[Bill Davy]

I did find a bug in the Cypress I2C code which resulted in this. Fix is
trivial, just stop the I2C when you see NACK:

void i2c_isr(void) interrupt I2C_VECT
{ // I2C State Machine
if(I2CS & bmBERR)
{
I2CPckt.status = I2C_BERROR;
}
else if ((!(I2CS & bmACK)) && (I2CPckt.status != I2C_RECEIVING))
{
I2CPckt.status = I2C_NACK;
I2CS |= bmSTOP; // RWD 8 June, 2005
}
else
....

Of course, not the whole solution, but every little helps.

Bill

"Richard Henry" <rphenry@home.com> wrote in message
news:3iiq6fFlp5huU1@individual.net...

I have noticed while checking out a prototype board that the I2C devices
occasionally hang the bus (SDA held low) preventing any further bus
transactions. My only fix is to cycle power to the board. That leads me
to
wonder whether adding a fet power switch feeding the I2C devices
controlled
by the micro might be of benefit - when the micro detects a hung bus, it
can
"reset" the I2C devices.

Anyone ever have to do this?

 

[Bob Monsen]

Richard Henry wrote:

I have noticed while checking out a prototype board that the I2C devices
occasionally hang the bus (SDA held low) preventing any further bus
transactions. My only fix is to cycle power to the board. That leads me to
wonder whether adding a fet power switch feeding the I2C devices controlled
by the micro might be of benefit - when the micro detects a hung bus, it can
"reset" the I2C devices.

Anyone ever have to do this?

This is usually a deadlock, caused by improper master control of the
bus. Usually, the slave is waiting for you to clock something, and you
are waiting for the slave to do something. If, for example, you forget
to NACK the last read, you can get stuck in a state in which the slave
thinks it's still talking.

If this is happening, clocking the bus will eventually cause the slave
to release SDA, because it wants to see your ack after 8 bits. If you
leave SDA alone, it'll think it's a nack, and stop trying to write data
to you.

If the slave is holding SCL low, you are probably screwed.

If the slave devices have a reset, use that instead of power. The FET
thing makes sense if there isn't a reset pin. Note that if the device
doesn't take too much power, you can just run it off of the
microcontroller pin. I believe PICs have a limit of 20mA, which may be
fine. I've done this with LCD displays before with no problem.

--
Regards,
Bob Monsen

If a little knowledge is dangerous, where is the man who has
so much as to be out of danger?
Thomas Henry Huxley, 1877