i2c Bus

[sofi]

hallo all ,
i am a beginner in vhdl , i need help .
i just want to ask with VHDL code wether the i2c Bus is free.
bus is free when a stop condition is sent und known start condition is sent


this is a start condition

______
scl(1)
__
\__
sda(1->0)

this is a stop condition

______
scl(1)
__
__/
sda(0->1)



please help me .
thanks

 

[Charles Bailey]

I think what you are asking for is a falling edge detector and a rising
edge detector.

Very simple:
SIGNAL sda1, sda2, falling_edge, rising_edge : std_logic;
BEGIN

proc1: PROCESS
BEGIN
WAIT until clk='1';
sda1 <= sda;
sda2 <= sda1;
END PROCESS;

falling_edge <= not sda1 and sda2;
rising_edge <= sda1 and not sda2;



"sofi" <sofien@gmx.de> wrote in message
news:116b91d5.0405130040.a143160@posting.google.com...

hallo all ,
i am a beginner in vhdl , i need help .
i just want to ask with VHDL code wether the i2c Bus is free.
bus is free when a stop condition is sent und known start condition is
sent


this is a start condition

______
scl(1)
__
\__
sda(1->0)

this is a stop condition

______
scl(1)
__
__/
sda(0->1)



please help me .
thanks

 

[sofi]

thanks