W
Weng Tianxiang
Guest
Hi,
I am programming DALLAS Maxim DS1374 2-wire, 32-bit binary count RTC.
Here is its specs on "Acknowledge":
Acknowledge: Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each byte. The master
device must generate an extra clock pulse that is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the
acknowledge clock pulse in such a way that the SDA line is stable low
during the high period of the acknowledge-related clock pulse. Setup
and hold times must be considered. A master must signal an end of data
to the slave by not generating an acknowledge bit on the last byte that
has been clocked out of the slave. In this case, the slave must leave
the data line high to enable the master to generate the STOP condition.
The problem is how to implement:
A master must signal an end of data to the slave by NOT GENERATING AN
ACKNOWLEDGE BIT ON THE LAST BYTE THAT HAS BEEN CLOCKED OUT OF THE
SLAVE.
Does it mean master must output high during the acknowledge bit time
during which slave will pull it down to zero to show acknowledge bit of
zero? An odd situation where master is trying to keep it high while
slave is truing to keep it low!
Thank you.
Weng
I am programming DALLAS Maxim DS1374 2-wire, 32-bit binary count RTC.
Here is its specs on "Acknowledge":
Acknowledge: Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each byte. The master
device must generate an extra clock pulse that is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the
acknowledge clock pulse in such a way that the SDA line is stable low
during the high period of the acknowledge-related clock pulse. Setup
and hold times must be considered. A master must signal an end of data
to the slave by not generating an acknowledge bit on the last byte that
has been clocked out of the slave. In this case, the slave must leave
the data line high to enable the master to generate the STOP condition.
The problem is how to implement:
A master must signal an end of data to the slave by NOT GENERATING AN
ACKNOWLEDGE BIT ON THE LAST BYTE THAT HAS BEEN CLOCKED OUT OF THE
SLAVE.
Does it mean master must output high during the acknowledge bit time
during which slave will pull it down to zero to show acknowledge bit of
zero? An odd situation where master is trying to keep it high while
slave is truing to keep it low!
Thank you.
Weng