I/O on current FPGAs - deserialise first ??

[Thomas Womack]

Two common peripheral interfaces are Firewire (400Mbps or 800Mbps) and
USB2 (480Mbps). These are serial, so you've got incredibly high bit
rates on the incoming pins; significantly higher than the clock rates
of reasonable FPGAs.

Do there exist chips to convert an 800Mbps serial stream to a 50MHz
stream of 16-bit words, and what are they called? I imagine it's not
impractical to hook a couple of those and a couple of SRAMs to a
single FPGA, stream in the signal and then read out little bits of
it if you need to look in the stream for control signals.

The proposed application is wire-speed video capture to a Firewire
disc from a Firewire or USB2 camera, using an FPGA in the middle to do
the trivial things like dark-frame subtraction.

Tom

 

[Peter Alfke]

You can use the Mult-Gigabit Transceivers (MGTs) on any of the
Virtex-IIPro devices. They provide/accept LVDs signals between 622 Mbps
and 3.125 Gbbps.
What is your method for insuring input transitions? The MGTs perform
transparent 8B10B as an option, but if you do not like that, you must
somehow guarantee input transitions for data recovery. There must be
many alternatives at your relatively slow rate.
Peter Alfke
====================
Thomas Womack wrote:

Two common peripheral interfaces are Firewire (400Mbps or 800Mbps) and
USB2 (480Mbps). These are serial, so you've got incredibly high bit
rates on the incoming pins; significantly higher than the clock rates
of reasonable FPGAs.

Do there exist chips to convert an 800Mbps serial stream to a 50MHz
stream of 16-bit words, and what are they called? I imagine it's not
impractical to hook a couple of those and a couple of SRAMs to a
single FPGA, stream in the signal and then read out little bits of
it if you need to look in the stream for control signals.

The proposed application is wire-speed video capture to a Firewire
disc from a Firewire or USB2 camera, using an FPGA in the middle to do
the trivial things like dark-frame subtraction.

Tom

 

[Uwe Bonnes]

Thomas Womack <twomack@chiark.greenend.org.uk> wrote:
: Two common peripheral interfaces are Firewire (400Mbps or 800Mbps) and
: USB2 (480Mbps). These are serial, so you've got incredibly high bit
: rates on the incoming pins; significantly higher than the clock rates
: of reasonable FPGAs.

: Do there exist chips to convert an 800Mbps serial stream to a 50MHz
: stream of 16-bit words, and what are they called? I imagine it's not
: impractical to hook a couple of those and a couple of SRAMs to a
: single FPGA, stream in the signal and then read out little bits of
: it if you need to look in the stream for control signals.

There are the UTMI Phys chips for USB, e,g. Lucent USS2X1, NEC uPD720120,
Philips ISP1501 or as a system approach Cypres CY7C680XX

:...

Bye

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Jeff Cunningham]

Thomas Womack wrote:

Two common peripheral interfaces are Firewire (400Mbps or 800Mbps) and
USB2 (480Mbps). These are serial, so you've got incredibly high bit
rates on the incoming pins; significantly higher than the clock rates
of reasonable FPGAs.

Do there exist chips to convert an 800Mbps serial stream to a 50MHz
stream of 16-bit words, and what are they called? I imagine it's not
impractical to hook a couple of those and a couple of SRAMs to a
single FPGA, stream in the signal and then read out little bits of
it if you need to look in the stream for control signals.

The proposed application is wire-speed video capture to a Firewire
disc from a Firewire or USB2 camera, using an FPGA in the middle to do
the trivial things like dark-frame subtraction.

If you want to implement a firewire compatible interface in a FPGA you
should consider using a standard firewire phy chip (search T.I.), which
essentially does what you say, i.e. convert a fast serial stream to a
stream of bytes. It also handles firewire functions such as bus reset
and arbitration which involve analog comparators, PLLs and so forth. The
phy to link chip interface is standardized and well documented. With an
external phy you would "only" have to implement the link level and maybe
some transaction level functions in the FPGA.

I am somewhat dissapointed that I have never seen any viable 3rd party
FPGA IP for the firewire link function. Does anyone know of any such IP
available now or on the horizon?

Jeff

 

[Mike Treseler]

Jeff Cunningham wrote:

I am somewhat dissapointed that I have never seen any viable 3rd party
FPGA IP for the firewire link function. Does anyone know of any such IP
available now or on the horizon?

Maybe one of these?
http://www.google.com/search?q=firewire+link+layer+synthesizable+core+2003

-- Mike Treseler

 

[Jeff Cunningham]

Mike Treseler wrote:

Jeff Cunningham wrote:

I am somewhat dissapointed that I have never seen any viable 3rd party
FPGA IP for the firewire link function. Does anyone know of any such
IP available now or on the horizon?


Maybe one of these?
http://www.google.com/search?q=firewire+link+layer+synthesizable+core+2003

-- Mike Treseler

I think those links all refer to IP that I would call "asic" flavored,
by which I mean it has been synthesized using synopsis design compiler
and any targeting of fpgas is a non-optimized prototyping port. I have
not done exhaustive checking, but I get the idea these are very
expensive. The open cores one is only in the early planning stage.

What I would like to see is a 1394 link function available in something
like the xilinx alliance core program - where I can assume the heavy
lifting of optimizing the design for fpga implementation and proving it
out has been done, i.e. where the risk would be similar to using the
alliance core pci interface for example. And where the cost would be in
a similar ball park.

Jeff