I need your help. (xor with d-ff)

[flowrian]

module p_odd (y, d_in, clk, rst);
input clk,rst,d_in;
output y;

reg y;
wire w1,d;

always @(posedge clk or negedge rst)
begin
w1 <= y^d_in;
d <= w1;
if (!rst)
y = 0;
else
y <= d;
end
endmodule

I don't know where it is wrong.
Show this picture. plz.

http://www.clien.net/zboard/data/kin/dff.gif

 

[Michael]

module p_odd (y, d_in, clk, rst);
input clk,rst,d_in;
output y;

reg y;

always @(posedge clk or negedge rst)
begin
if (!rst)
y = 0;
else
y <= y ^ d_in;
end
endmodule

 

[Ron]

How about?

module p_odd (y, d_in, clk, rst);
input clk,rst,d_in;
reg D;
output reg y;

always @(posedge clk)
if (rst)
begin
y<= 0;
D<= 0;
end
else
begin
D<= y ^ d_in;
y<= D;
end
endmodule

 

[Michael]

bad idea: you'll have 2 FFs instead of one and your output will be
delayed by 1 additional clock. You also don't have async reset.