I need your help. (xor , d-ff)

[flowrian]

module p_odd (y, d_in, clk, rst);
input clk,rst,d_in;
output y;

reg y;
wire w1,d;

always @(posedge clk or negedge rst)
begin
w1 <= y^d_in;
d <= w1;
if (!rst)
y = 0;
else
y <= d;
end
endmodule


I don't know where it is wrong.

<a href ="http://www.clien.net/zboard/data/kin/dff.gif"
target="_blank">Please click this!</a>

 

[Jason Rosinski]

You can't treat wires like registers (even if it's a combinatorial process).

So try something like:

wire w1 = y^d_in;

always @(posedge clk or negedge rst)
if (!rst)
y &lt;= 0;
else
y &lt;= w1


flowrian wrote:

module p_odd (y, d_in, clk, rst);
input clk,rst,d_in;
output y;

reg y;
wire w1,d;

always @(posedge clk or negedge rst)
begin
w1 &lt;= y^d_in;
d &lt;= w1;
if (!rst)
y = 0;
else
y &lt;= d;
end
endmodule


I don't know where it is wrong.

a href ="http://www.clien.net/zboard/data/kin/dff.gif"
target="_blank"&gt;Please click this!&lt;/a

 

[John_H]

flowrian wrote:

module p_odd (y, d_in, clk, rst);
input clk,rst,d_in;
output y;

reg y;
wire w1,d;

always @(posedge clk or negedge rst)
begin
w1 &lt;= y^d_in;
d &lt;= w1;
if (!rst)
y = 0;
else
y &lt;= d;
end
endmodule


I don't know where it is wrong.

Your always block is written to be executed whenever clk rises or rst
drops. If rst drops, you're assigning w1 and d with the same value as
if it's the rising edge of clk. You're asking the synthesizer or
simulator to give you w1 and d controlled by two clocks.

If you want an async reset, everything in the always block should have
an if(!rst) clause. If you want the synchronous reset, remove the "or
negedge rst" from your sensitivity list.

Oh, also. Wow. w1 and d are getting assigned as if they are registers.
Either declare the values as registers or - if your intent was that
they be combinatorial - take them out of the clocked always block and
use the assign.

So - do you want async reset? Do you want everything registered?