I need some help here.

S

Scott Wiper

Guest
I must apologise for this cross posting.

I am stumpted on why this one is not working...

I have checked with my logic probe and my frequency meter. I see the frequency at 2.456MHZ at the clock oscillator and The second part I am getting a breif pulse of 1 HZ at pint 2 on the 4024 to which is carried to pin 10 of the second 4020. The time IC should close the relay for 1 second every hour but it's not doing this and U13 that is not shown on this image. and why the 74ls273 is not being clocked even though the pulse signal is present on pin 1 of the third 4024. The time is for a mechanical totaliser to count hours of opperation.


Please help with this one. I have had some exellent help with other project on these groups. Your input on this problem would be most helpfull. If you need to contact me privately. Please ise the link below.

The image is here for you to review. http://www.travel-net.com/~swiper/7000.gif

--
My cat Tigger says every morning...
"Before my morning coffee... I might as well be a dog!"
To contact folow the link below.
http://www.travel-net.com/~swiper/email.htm
 
On Thu, 25 Mar 2004 14:37:35 -0500, "Scott Wiper"
<nobody@devnull.spamcop.met> wrote:

I must apologise for this cross posting.

I am stumpted on why this one is not working...

I have checked with my logic probe and my frequency meter. I see the frequency at 2.456MHZ at the clock oscillator and The second part I am getting a breif pulse of 1 HZ at pint 2 on the 4024 to which is carried to pin 10 of the second 4020. The time IC should close the relay for 1 second every hour but it's not doing this and U13 that is not shown on this image. and why the 74ls273 is not being clocked even though the pulse signal is present on pin 1 of the third 4024. The time is for a mechanical totaliser to count hours of opperation.


Please help with this one. I have had some exellent help with other project on these groups. Your input on this problem would be most helpfull. If you need to contact me privately. Please ise the link below.

The image is here for you to review. http://www.travel-net.com/~swiper/7000.gif
Click to expand...
"The page cannot be found"

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

Throughout the history of this great country there have actually
been people of only two political persuasions: fighters and cowards.
WE MUST NOT LET THE LATTER PREVAIL IN THE NEXT ELECTION!
 
Hi. I only took a brief look at the circuit diagram you posted, but
there's something odd about the RST line. Where it goes near U2 and U3
it's shown as being tied to Vss, but if you close SW1 it'll be connected
to Vdd as well, causing a dead short across the power supply.

The reset pulses generated by U6 might be very narrow, too narrow
to reliably trigger the 555 or clock U5 or do whetever else they're
supposed to. You might try feeding the outputs of U6 through a
latch (perhaps another '273 clocked from the output of U2?) to
ensure that the reset pulse has a nice well defined width and see if
the problem goes away.

It looks like D2, D3, D5 are being used to implement 'wired-OR' logic, but
if e.g. U6 pin 6 is low but U6 pin 8 is high then they'll fight. You
need a resistor, more diodes, or (better) use real logic gates there.

By the way, please don't post in HTML --- lots of people (including me)
find it annoying and it really doesn't add anything to your post.
Scroll down to the bottom of this page ---
http://sc1.scconsult.com/~nnq/nhtml.html
--- for instructions on how to turn it off.

--
Wim Lewis <wiml@hhhh.org>, Seattle, WA, USA. PGP keyID 27F772C1
 
"Wim Lewis" <wiml@underhill.hhhh.org> wrote in message
news:c3vfhk$fl2$0@216.39.137.58...

Hi. I only took a brief look at the circuit diagram you posted, but
there's something odd about the RST line. Where it goes near U2 and U3
it's shown as being tied to Vss, but if you close SW1 it'll be connected
to Vdd as well, causing a dead short across the power supply.

The only IC,s being reset is U2, U3 and U5. U13 which is new is another
74ls273 that is clocked by u3 that is 50%. duty cycle. U5 is now clocked off
U13 so it should be .5HZ duty cycle that should reliably clock the 555 that
drives the totaliser and U8 and U9 The reset R/C is to sync and SW1 is a
momentary nomally open and C3 is to remove switch bounce.

I have uploaded before I posted so you can see the chamges.

http://www.travel-net.com/~swiper/7000.gif




--
My cat Tigger says every morning...
"Before my morning coffee... I might as well be a dog!"
To contact folow the link below.
http://www.travel-net.com/~swiper/email.htm
 
I must apologise for this cross posting.

I am stumpted on why this one is not working...

I have checked with my logic probe and my frequency meter. I see the frequency at 2.456MHZ at the clock oscillator and The second part I am getting a breif pulse of 1 HZ at pint 2 on the 4024 to which is carried to pin 10 of the second 4020. The time IC should close the relay for 1 second every hour but it's not doing this and U13 that is not shown on this image. and why the 74ls273 is not being clocked even though the pulse signal is present on pin 1 of the third 4024. The time is for a mechanical totaliser to count hours of opperation.


Please help with this one. I have had some exellent help with other project on these groups. Your input on this problem would be most helpfull. If you need to contact me privately. Please ise the link below.

The image is here for you to review. http://www.travel-net.com/~swiper/7000.gif

--
My cat Tigger says every morning...
"Before my morning coffee... I might as well be a dog!"
To contact folow the link below.
http://www.travel-net.com/~swiper/email.htm

One thing I see obvious is you dont have any .1 uf caps on the power<>ground pins of the chips. Without these then your clock pulses will show up on the power rail and cause many problems with timing.
Also the reset switch when pushed, supplies +5 volt to some outputs on gates that may be at a low state, thus cuasing them to source full current and burnout. Try adding a current limit resistor valued to the source capacity of the gates. fwiw..
 
Scott Wiper wrote:
I must apologise for this cross posting.

I am stumpted on why this one is not working...

I have checked with my logic probe and my frequency meter. I see the
frequency at 2.456MHZ at the clock oscillator and The second part I am
getting a breif pulse of 1 HZ at pint 2 on the 4024 to which is carried
to pin 10 of the second 4020. The time IC should close the relay for 1
second every hour but it's not doing this and U13 that is not shown on
this image. and why the 74ls273 is not being clocked even though the
pulse signal is present on pin 1 of the third 4024. The time is for a
mechanical totaliser to count hours of opperation.


Please help with this one. I have had some exellent help with other
project on these groups. Your input on this problem would be most
helpfull. If you need to contact me privately. Please ise the link below.

The image is here for you to review.
http://www.travel-net.com/~swiper/7000.gif

--
Click to expand...
The circuit has a multitude of logic family incompatibilities, design
errors, and drawing inaccuracies. The specific problem you mention about
the brief RST pulse to the 4024 U4 pin 2 but no clock through to the
LS273 U13 Q0 pin 2, is caused by the fact that the 4024 advances on CLK
negative edge whereas the LS273 clocks on the positive going edge. The
sequence is therefore 4017 U3 advances to state Q5, U3 COUT transitions
LOW, 4024 U4 clocks, U6 AND goes HIGH, U4 is RST, U6 AND goes LOW and
stays there for the next U13 CLK positive edge occurring 5 U3 clock
cycles later- so that U13 Q0 is locked on LOW and is never HIGH. You
might use the LS273 Q0 output for that RST and not the LS21- but I
hesitate to recommend any alterations whatsoever.
What's with the LDR and thermistor inputs? Your LM1458's may be
misapplied also. It would help if you summarize the overall functional
theory of operation of what you are attempting to accomplish without
referring to that circuit, and then we may be able to suggest more
conventional means of approach.
 
in article 9yG8c.10367$kc2.242749@nnrp1.uunet.ca, Scott Wiper at
nobody@devnull.spamcop.met wrote on 3/25/04 13:37:

I must apologise for this cross posting.

I am stumpted on why this one is not working...

I have checked with my logic probe and my frequency meter. I see the
frequency at 2.456MHZ at the clock oscillator and The second part I am
getting a breif pulse of 1 HZ at pint 2 on the 4024 to which is carried to
pin 10 of the second 4020. The time IC should close the relay for 1 second
every hour but it's not doing this and U13 that is not shown on this image.
and why the 74ls273 is not being clocked even though the pulse signal is
present on pin 1 of the third 4024. The time is for a mechanical totaliser
to count hours of opperation.


Please help with this one. I have had some exellent help with other project
on these groups. Your input on this problem would be most helpfull. If you
need to contact me privately. Please ise the link below.

The image is here for you to review.
http://www.travel-net.com/~swiper/7000.gif

Out of curiosity, why is U2 pin 11 (reset) tied high?
 
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