Jan 11, 2006 #1 A apssingh Guest I wand document and and idea for ram coding and verification with timing cycles included. plz send it in verilog.
I wand document and and idea for ram coding and verification with timing cycles included. plz send it in verilog.
Jan 11, 2006 #2 A Ajeetha Guest Hi, Why not ask for that in comp.lang.verilog then? Also, a simple RAM will be: reg [31:0] ram [7:0]; Timing etc. - why not refer to a standard data sheet? Ajeetha www.noveldv.com
Hi, Why not ask for that in comp.lang.verilog then? Also, a simple RAM will be: reg [31:0] ram [7:0]; Timing etc. - why not refer to a standard data sheet? Ajeetha www.noveldv.com
