I have some doubts in verilog

hi every body,

I have some doubts in verilog. Please clear my doubts.

1. How to declare arrays with each element in the array is a vector.

2. Can input and output ports can be real, integer etc., If yes, How?
If no, then how can we pass floating point values to a module.

3. what are the default of value of REAL and INTEGER variables.

Thanks 'n' regards
Prash


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[NigelE]

On Apr 27, 12:42 pm, 'use_real_email' wrote:

hi every body,

I have some doubts in verilog. Please clear my doubts.

1. How to declare arrays with each element in the array is a vector.

2.  Can input and output ports can be real, integer etc., If yes, How?
If no, then how can we pass floating point values to a module.

3. what are the default of value of REAL and INTEGER  variables.

Thanks 'n' regards
Prash

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1. You use the packed dimension to set the vector width and the
unpacked one to set the array size
eg reg [7:0] r1 [1:256] is a 256 array of 8 bit vectors

2. In verilog, only net types can be input ports eg wires, so you
can't use real as a input port since it is a variable type
SystemVerilog relaxes this, allowing variable data types as input
ports eg

module top;
real r; // variable types can be used in netlist
real_out ro (.r);
real_in ri (.r);
endmodule

module real_out(output real r); // output is real variable
type
initial begin
r = 3.14159265;
#1;
r = 3.14159265 * 2;
end
endmodule

module real_in(input real r); // input is real variable
type
always@(r)
$display("r = %f",r);
endmodule

3. The default value for 2 state types (real, int, bit) is 0
The default value for 4 state types (integer, logic) is X

Cheers

- Nigel

 

[Gabor]

On 3/30/2013 10:36 AM, exam123321@gmail.com wrote:

I've been working on my final year project which is based on hardware implementation of Image Encryption and I am finding a problem dealing with the matrix of the image. I have tried few ways, but the problem still persists.

The problem is:
I have an image (256 level -gray scale) stored in a 1-D Array (as 2-D array is not supported in I-VERILOG). I need to take some particular pixels in a particular order, for example:

@(posedge clk)
begin
M1<=Image[24*k+7:24*k];
M2<=Image[24*k+15:24*k+8];
M3<=Image[24*k+23:24*k+16];
end

where k and M1,M2,M3 are register data-type,and k is increasing at every clock pulse.(counter)

But on compiling, one of the errors is as shown :
Part select expressions must be constant.
This msb expression violates the rule: (('sd24)*(k))+('sd23)

The other error messages are similar. I even tried for loop for the same. But the same error persists.
What can be the other way to select a particular range of elements of an array and give it to a register? It will be really grateful if you can help me about the same.

I'm using I-VERILOG

I'm a little confused here. You say Image is a 1D array. Array of
what? If you've defined it for example as:

reg [7:0] Image [0:4095];

Then it doesn't make sense for an assignment to take a range from Image.

If you really meant it is a vector as in:

reg [8*4096-1:0] Image;

Then you could do what you want using the standard range format like:

M1 <= Image[24*k +: 8];

But that's only if I-VERILOG supports it. If I remember correctly
this syntax was added in Verilog 2001. You say that loops didn't work.
Can you post what you tried?

-- Gabor

 

On Monday, April 27, 2009 5:12:28 PM UTC+5:30, 'use_real_email' wrote:

hi every body,

I have some doubts in verilog. Please clear my doubts.

1. How to declare arrays with each element in the array is a vector.

2. Can input and output ports can be real, integer etc., If yes, How?
If no, then how can we pass floating point values to a module.

3. what are the default of value of REAL and INTEGER variables.

Thanks 'n' regards
Prash


--
prashaiit
------------------------------------------------------------------------
prashaiit's Profile: http://www.fpgacentral.com/group/member.php?userid=65
View this thread: http://www.fpgacentral.com/group/showthread.php?t=89680

I've been working on my final year project which is based on hardware implementation of Image Encryption and I am finding a problem dealing with the matrix of the image. I have tried few ways, but the problem still persists.

The problem is:
I have an image (256 level -gray scale) stored in a 1-D Array (as 2-D array is not supported in I-VERILOG). I need to take some particular pixels in a particular order, for example:

@(posedge clk)
begin
M1<=Image[24*k+7:24*k];
M2<=Image[24*k+15:24*k+8];
M3<=Image[24*k+23:24*k+16];
end

where k and M1,M2,M3 are register data-type,and k is increasing at every clock pulse.(counter)

But on compiling, one of the errors is as shown :
Part select expressions must be constant.
This msb expression violates the rule: (('sd24)*(k))+('sd23)

The other error messages are similar. I even tried for loop for the same. But the same error persists.
What can be the other way to select a particular range of elements of an array and give it to a register? It will be really grateful if you can help me about the same.

I'm using I-VERILOG