S
somayeh2010
Guest
This is my testbench code.
When I load it and want see signals in wave, after I add it, wave i
empty.
I do everything but the problem isn't solve.
Can anyone help me?
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity test_dff is
end test_dff;
architecture behavioral of test_dff is
component dff
port(din,clk,rst:in std_logic;
doutut std_logic);
end component;
signal clk1:std_logic:='0';
signal rst1:std_logic:='0';
signal din1:std_logic;
signal dout1:std_logic;
begin
unit0: dff port map(din=>din1,clk=>clk1,rst=>rst1,dout=>dout1);
process
begin
din1<='0';
wait for 100 ns;
din1<='1';
wait for 100 ns;
din1<='0';
wait for 100 ns;
din1<='1';
wait for 100 ns;
end process;
clock: process
begin
clk1<=not clk1 after 25 ns;
wait for 50 ns;
end process clock;
stimulus: process
begin
wait for 5 ns; rst1<='1';
wait for 4 ns; rst1 <='0';
wait;
end PROCESS stimulus;
end behavioral;
---------------------------------------
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When I load it and want see signals in wave, after I add it, wave i
empty.
I do everything but the problem isn't solve.
Can anyone help me?
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity test_dff is
end test_dff;
architecture behavioral of test_dff is
component dff
port(din,clk,rst:in std_logic;
doutut std_logic);
end component;
signal clk1:std_logic:='0';
signal rst1:std_logic:='0';
signal din1:std_logic;
signal dout1:std_logic;
begin
unit0: dff port map(din=>din1,clk=>clk1,rst=>rst1,dout=>dout1);
process
begin
din1<='0';
wait for 100 ns;
din1<='1';
wait for 100 ns;
din1<='0';
wait for 100 ns;
din1<='1';
wait for 100 ns;
end process;
clock: process
begin
clk1<=not clk1 after 25 ns;
wait for 50 ns;
end process clock;
stimulus: process
begin
wait for 5 ns; rst1<='1';
wait for 4 ns; rst1 <='0';
wait;
end PROCESS stimulus;
end behavioral;
---------------------------------------
Posted through http://www.FPGARelated.com