I have a pb to read from file

[sky_nad]

Hi,

I need ur help in my VHDL design:i wanted to read the datas of
component Ram ( data_in) from a file for after use them in this Ram
but when i simulated my code i could find my datas from a file but the
result ( data_out) in output Ram was the first data from file only.I
don't know why. Could u help me for resolving my problem?

This is my code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;

entity ram_tb1 is
generic(DEEP: integer := 4;
WIDTH:integer := 8);
port(wr,clk:std_logic;
adram:in std_logic_vector (DEEP downto 1);
data_in: inout std_logic_vector(WIDTH downto 1);
data_outut std_logic_vector(WIDTH downto 1));
end ram_tb1;
architecture bev_tb1 of ram_tb1 is

component ram
generic(DEEP: integer := 4;
WIDTH:integer := 8);
port(wr,clk:std_logic;
adram:in std_logic_vector (DEEP downto 1);
data_in: in std_logic_vector(WIDTH downto 1);
data_outut std_logic_vector(WIDTH downto 1));
end component;


file from_file:text open READ_MODE is "ram_test_rd.txt";
-- file to_text:text open WRITE_MODE is "ram_test_wr.txt";

begin
call_ram: ram generic map ( deep => 4,
width=> 8)
port map(clk=>clk,
wr=>wr,
adram=>adram,
data_in=>data_in,
data_out=>data_out);

process
variable buf_out,buf_in:line;
variable to_data: bit_vector(8 downto 1);

begin

while not endfile(from_file) loop
wait until rising_edge (clk) ;

-- read digital data from input file
readline(from_file, buf_out);
read(buf_out, to_data);
data_in <= to_stdlogicvector(to_data);

end loop;
end process;

end;


The file "ram_test_rd.txt":

00110011
01010101
00001111

control file is:
force clk 0 0, 1 10, 0 20, 1 30, 0 40, 1 50, 0 60, 1 70, 0 80, 1 90, 0
100, 1 110, 0 120, 1 130, 0 140, 1 150, 0 160
force wr 1 0, 0 70
force adram 0 10, 1 30, 2 50,0 70,1 90,2 110
run 200

Thanks and best regards.