I can't convert vector to integer.

[ąčÁžÁř]

Array has a parameter as integer.
But I have a vector data.

I can't convert vector to integer.

Help me.

 

[SneakerNet]

"ąčÁžÁř" <whois001@hotmail.com> wrote in message
news:boc5r3$2to$1@news1.kornet.net...

Array has a parameter as integer.
But I have a vector data.

I can't convert vector to integer.

Help me.

have you tried this?
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY adder IS
PORT (op1, op2 : IN UNSIGNED(7 DOWNTO 0);
result : OUT INTEGER);
END adder;

ARCHITECTURE maxpld OF adder IS
BEGIN
result <= CONV_INTEGER(op1 + op2);
END maxpld;

 

[Matt North]

"SneakerNet" <nospam@nospam.org> wrote in message
news:cviqb.9967$Mn.254473@news.xtra.co.nz...

"ąčÁžÁř" <whois001@hotmail.com> wrote in message
news:boc5r3$2to$1@news1.kornet.net...
Array has a parameter as integer.
But I have a vector data.

I can't convert vector to integer.

Help me.



have you tried this?
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY adder IS
PORT (op1, op2 : IN UNSIGNED(7 DOWNTO 0);
result : OUT INTEGER);
END adder;

ARCHITECTURE maxpld OF adder IS
BEGIN
result <= CONV_INTEGER(op1 + op2);
END maxpld;

Or:
LIBRARY ieee;

USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity ent is
generic(asize: integer:= 8);
port(vector_in: in std_logic_vector(asize-1 downto 0);
intconv : out integer);
end ent;

architecture rtl of ent is
begin
intconv<=to_integer(unsigned(vector_in));
end rtl;

 

[Neil Zanella]

Hello,

In VHDL, there always seem to be zillions of ways if doing the same thing.
Perhaps this is because VHDL is a modelling language. When it comes to
synthesis though, the same components present in the hardware end up
being the ones used, so it seems almost like it is to some extent
irrelevant how some particular functionality is modeled, so long
as the model can be synthesized on the target device, which
in most cases, AFAIK, consists of an FPGA or CPLD.

For instance, it is not clear to me when integer should be used, and when
vector should be used. It seems that one advantage of using integers is to
be able to address arrays. It is also not clear to me when the dataflow
model of VHDL programming is to be preferred over the sequential one,
and vice versa.

Furthermore, it is not clear whether VHDL is a truly useful tool in a
programmer's toolbox. For instance many embedded devices can be
programmed in conventional programming languages such as C.
I would like to see some practical applications of VHDL.

Where exactly is VHDL used? And is much designing whith
VHDL required in the real world? Who are the main users
of VHDL? Who is the community of VHDL users and what
are most VHDL users' goals when learning VHDL?

Are there any significanltly complex free VHDL designs out there,
in the same way several free software packages written in other
languages can be found complete with source code on the web?

Thank you for your responses,

Basically, I am sort of curious to learn about what people are really
doing with VHDL and whether VHDL programming plays a major or minor
role in it.

Thanks,

Neil

 

[David R Brooks]

Modern VLSI (ASIC or FPGA) designs are almost exclusively designed in
HDLs: either VHDL or Verilog. VHDL derives from Ada, while Verilog
derives from C.
Both are widely used, but there seems to be a preponderance of
Verilog in the US, and VHDL in the rest of the world.
As to what language constructs to use for the synthesiser, your
synthesiser should come with a manual giving recommendations. For
example, the Xilinx tool XST has the "XST User Guide", which
essentially answers questions of "I want to create ... logic, what's
the best HDL to write?"
There is a pool of free HDL designs at www.opencores.org

Neil Zanella <nzanella@cs.mun.ca> wrote:

:
:Hello,
:
:In VHDL, there always seem to be zillions of ways if doing the same thing.
erhaps this is because VHDL is a modelling language. When it comes to
:synthesis though, the same components present in the hardware end up
:being the ones used, so it seems almost like it is to some extent
:irrelevant how some particular functionality is modeled, so long
:as the model can be synthesized on the target device, which
:in most cases, AFAIK, consists of an FPGA or CPLD.
:
:For instance, it is not clear to me when integer should be used, and when
:vector should be used. It seems that one advantage of using integers is to
:be able to address arrays. It is also not clear to me when the dataflow
:model of VHDL programming is to be preferred over the sequential one,
:and vice versa.
:
:Furthermore, it is not clear whether VHDL is a truly useful tool in a
rogrammer's toolbox. For instance many embedded devices can be
rogrammed in conventional programming languages such as C.
:I would like to see some practical applications of VHDL.
:
:Where exactly is VHDL used? And is much designing whith
:VHDL required in the real world? Who are the main users
f VHDL? Who is the community of VHDL users and what
:are most VHDL users' goals when learning VHDL?
:
:Are there any significanltly complex free VHDL designs out there,
:in the same way several free software packages written in other
:languages can be found complete with source code on the web?
:
:Thank you for your responses,
:
:Basically, I am sort of curious to learn about what people are really
:doing with VHDL and whether VHDL programming plays a major or minor
:role in it.
:
:Thanks,
:
:Neil

 

[Thomas Stanka]

Hi,

Neil Zanella <nzanella@cs.mun.ca> wrote:

Perhaps this is because VHDL is a modelling language. When it comes to

This is an important fact for later on. It is important that you
understand the implications of this fact when speaking over VHDL.

For instance, it is not clear to me when integer should be used, and when
vector should be used. It seems that one advantage of using integers is to
be able to address arrays.

This is a matter of style and what you like to do with the signals.
If your creating a cirquit, when do you prefer single wire and when do
you prefer a ribbon cable?

It is also not clear to me when the dataflow

model of VHDL programming is to be preferred over the sequential one,
and vice versa.

This is something complete different. Is your HW combinatorial or
sequential it's a matter of your desired HW.

Furthermore, it is not clear whether VHDL is a truly useful tool in a
programmer's toolbox. For instance many embedded devices can be
programmed in conventional programming languages such as C.
I would like to see some practical applications of VHDL.

VHDL is not useful for programmers but for HW developing. Don't try
programming in VHDL (first you may lack some statements but mainly you
won't be able to do HW when thinking of a programming language when
doing VHDL).

Where exactly is VHDL used? And is much designing whith
VHDL required in the real world? Who are the main users
of VHDL? Who is the community of VHDL users and what
are most VHDL users' goals when learning VHDL?

VHDL is one of two common _description_ languages doing FPGA or ASIC
design (Verilog is the second, some other languages are less important
nowadays).
VHDL is also used for testbenches to test a HW-description through
simulation which is pretty close to programming normal SW.
VHDL is used for a lot of Fpga and Asic designs, maybe the
intelligence of your mobile, some ICs in your computer, car or
anywhere else you need application specific logic.

Are there any significanltly complex free VHDL designs out there,
in the same way several free software packages written in other
languages can be found complete with source code on the web?

Yes. Search Google for "VHDL core [open|free]".