How/when are defparams applied?

M

Mike Pearson

Guest
My vendor has given me a netlist which I'm trying to run a timing sim
on. Most of the timing is in an sdf file, but the vendor has supplied
a Verilog file containing defparams for the memory timings.

The problem is, these defparams are specified on a full hierarchical
path, and I'm not sure how to get them into the simulation. The
compiler doesn't know about the full path when compiling a given
module, so I presumably have to specify this file after elaboration,
but I can't see how.

Can anyone enlighten me? I'm using ModelSim.

Thanks -

Mike
 
Just apply your path.

Mike Pearson wrote:
My vendor has given me a netlist which I'm trying to run a timing sim
on. Most of the timing is in an sdf file, but the vendor has supplied
a Verilog file containing defparams for the memory timings.

The problem is, these defparams are specified on a full hierarchical
path, and I'm not sure how to get them into the simulation. The
compiler doesn't know about the full path when compiling a given
module, so I presumably have to specify this file after elaboration,
but I can't see how.

Can anyone enlighten me? I'm using ModelSim.

Thanks -

Mike
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