how using files as input and outputs

[beginner_vhdl]

hi everybody,
i want to use files as input and an output for my vhdl program
for example as a program i have :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity entier is
Port ( clk : in STD_LOGIC;
en : in STD_LOGIC_VECTOR (7 downto 0);
sor : out STD_LOGIC_VECTOR (7 downto 0)
);
end entier ;

architecture Behavioral of entier is
begin
sor <= en;
end Behavioral;
------------------------------------------------------------------------------
i want that my inputs ( en ) are from a file and my outputs saved
into a file ( sor)
thank you for your help

 

[chuck10000]

Hi Beginner_vhdl,

I am wondering what you are really trying to do?
Which files are you talking about?

Do you mean that you would like to simulate your entity on a computer
before using it on your hardware target?

Regards,
Chuck.
bananASK me all your questions on http://www.bananask.com/ask_Chuck123

On 30 avr, 13:52, beginner_vhdl <abai...@gmail.com> wrote:

hi everybody,
i want to use files as input and an output for my vhdl program
for example as a program i have :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity entier is
Port ( clk : in STD_LOGIC;
en : in STD_LOGIC_VECTOR (7 downto 0);
sor : out STD_LOGIC_VECTOR (7 downto 0)
);
end entier ;

architecture Behavioral of entier is
begin
sor <= en;
end Behavioral;
---------------------------------------------------------------------------­---
i want that my inputs ( en ) are from a file and my outputs saved
into a file ( sor)
thank you for your help

 

[beginner_vhdl]

On 30 avr, 15:36, chuck10000 <c...@cactusnet.be> wrote:

Hi Beginner_vhdl,

I am wondering what you are really trying to do?
Which files are you talking about?

Do you mean that you would like to simulate your entity on a computer
before using it on your hardware target?

Regards,
Chuck.
bananASK me all your questions onhttp://www.bananask.com/ask_Chuck123

On 30 avr, 13:52, beginner_vhdl <abai...@gmail.com> wrote:
hi , for me i want to simulate my entity on a computer before using hardware target , that it is why i m asking about using files on vhdl
hi everybody,
i want to use files as input and an output for my vhdl program
for example as a program i have :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity entier is
Port ( clk : in STD_LOGIC;
en : in STD_LOGIC_VECTOR (7 downto 0);
sor : out STD_LOGIC_VECTOR (7 downto 0)
);
end entier ;

architecture Behavioral of entier is
begin
sor <= en;
end Behavioral;
---------------------------------------------------------------------------­­---
i want that my inputs ( en ) are from a file and my outputs saved
into a file ( sor)
thank you for your help