how to write tri-state bus in rtl

[mynewlifever@yahoo.com.cn]

how to write available tri-state?I saw some code write like this:
assign con_in = control; //control is the
tri-state bus
assign control = en?con_out:1:bz; //en is the enable signal
Does all the tri-state bus is open-drain?
Does all the tri-state bus need to be pull up outside the chip?

Thank you!

 

[gabor]

mynewlifever@yahoo.com.cn wrote:

how to write available tri-state?I saw some code write like this:
assign con_in = control; //control is the
tri-state bus
assign control = en?con_out:1:bz; //en is the enable signal

above line should be:

assign control = en?con_out:1'bz; //en is the enable signal

Does all the tri-state bus is open-drain?

I would say not, but it depends on your en function. If
en is only active while con_out is 0, then you would have
open drain (sort of .. could be implementation dependent,
i.e. en gating could cause a high glitch if en path is slow).
for example the following code could cause a brief high
drive output if the AND gate for en is slow and
master_enable stays on during a rising edge of con_out:

assign en = !con_out & master_enable;
assign control = en?con_out:1'bz;

More typically open drain is implemented like

assign control = en ? 1'b0 : 1'bz;

This has no chance of driving high (two choices are
0 or highZ).

Does all the tri-state bus need to be pull up outside the chip?

Not sure what you mean by "all the tri-state bus", since your bus
width appears to be 1 bit ("1'bZ"). But external pull-up would be
necessary for open drain, or if the bus is left un-driven for long
periods of time and the chip has no internal (weak) pull-up.

Thank you!

 

[mynewlifever@yahoo.com.cn]

Gabor,thank you for you response,I still have some question.
(1)

assign en = !con_out & master_enable;
assign control = en?con_out:1'bz;
Did you mean output signal control is controlled by both en and

master_enable signal?
(2)
Can you give me some advice on how to write bi-direction data
bus?And if bi-direction data bus does not need extenal pull-up?
I am puzzled about this kind of bus.At first,I think
bi-direction data bus == thr-state bus(I mean the bus like scl or
sda).But after read what you say,I think I confused these two
conception.Please give me some detail instruction.
English is not my native language.I hope I have already expressed
clearly.
Thank you for you help!