How to write the modular code?

[Lee]

Dear all,

I have the following code,

module model_proto;
.....
endmodule

module test;

model_proto inst 1
..
..
..
model_proto inst n

endmodele

Here, can I make n as flexible number (variable). When I call the
module in the other module, I can initialize n.

I need a module that have different number of instances. I don't like
to maintain two or more files. How can I make it?

Thanks,

Adrian

 

[Tom Hawkins]

yxl4444@louisiana.edu (Lee) wrote in message news:<5c3c88bc.0406191558.3bf9eb50@posting.google.com>...

Dear all,

I have the following code,

module model_proto;
....
endmodule

module test;

model_proto inst 1
.
.
.
model_proto inst n

endmodele

Here, can I make n as flexible number (variable). When I call the
module in the other module, I can initialize n.

I need a module that have different number of instances. I don't like
to maintain two or more files. How can I make it?

In Verilog, you'll have to use generate/endgenerate, which can get messy.

In Confluence, it's a simple recursive component:

component model_proto is
(* ... *)
end

component test +n is
if n > 0
{model_proto}
{test (n - 1)}
end
end


-Tom

Thanks,

Adrian

 

[Allan Herriman]

On 20 Jun 2004 13:02:05 -0700, tom1@launchbird.com (Tom Hawkins)
wrote:

yxl4444@louisiana.edu (Lee) wrote in message news:<5c3c88bc.0406191558.3bf9eb50@posting.google.com>...
Dear all,

I have the following code,

module model_proto;
....
endmodule

module test;

model_proto inst 1
.
.
.
model_proto inst n

endmodele

Here, can I make n as flexible number (variable). When I call the
module in the other module, I can initialize n.

I need a module that have different number of instances. I don't like
to maintain two or more files. How can I make it?

In Verilog, you'll have to use generate/endgenerate, which can get messy.

generate
genvar i;
for (i=1; i<=n; i=i+1) begin : must_have_label_here
model_proto inst ( ... );
end
endgenerate


I don't regard that as messy. I guess it's one of those "in the eye
of the beholder" things.


Regards,
Allan.

 

[Tom Hawkins]

Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message [snip]

I need a module that have different number of instances. I don't like
to maintain two or more files. How can I make it?

In Verilog, you'll have to use generate/endgenerate, which can get messy.


generate
genvar i;
for (i=1; i<=n; i=i+1) begin : must_have_label_here
model_proto inst ( ... );
end
endgenerate


I don't regard that as messy. I guess it's one of those "in the eye
of the beholder" things.

Your right, instantiating N number of modules is easy. The mess
usually comes with the wiring.

Also, what happens if the configuration parameters are more that just
simple integers? What if they're composite data-structures, groups of
systems, sets of components (aka modules), or preconfigured wiring
harnesses? Unfortunately, Verilog's generate features don't extend
far beyond for-loops and integer parameters.

In contrast to Verilog, Confluence was designed from the begining as a
parametric configuration language.

-Tom