How to write an "alias" statement

[Weng Tianxiang]

Hi,

I have a register array with each register having (pointer & data), now I hope to display each of two parts using 2 different names for easy reading in simulation.

Here is code defining the register array R:
type R_Type is array(0 to R_SIZE) of unsigned(POINTER_BITS + DATA_BITS-1 downto 0);
signal R : R_Type;
alias P1 : it shows R array part of (DATA_BITS-1 downto 0);
alias P2 : it shows R array part of (POINTER_BITS-1 downto DATA_BITS);

How to write the 2 alias statements in VHDL 2002 or 2008?

Thank you.

Weng

 

[Weng Tianxiang]

On Tuesday, December 4, 2018 at 12:37:54 PM UTC-8, Weng Tianxiang wrote:

Hi,

I have a register array with each register having (pointer & data), now I hope to display each of two parts using 2 different names for easy reading in simulation.

Here is code defining the register array R:
type R_Type is array(0 to R_SIZE) of unsigned(POINTER_BITS + DATA_BITS-1 downto 0);
signal R : R_Type;
alias P1 : it shows R array part of (DATA_BITS-1 downto 0);
alias P2 : it shows R array part of (POINTER_BITS-1 downto DATA_BITS);

How to write the 2 alias statements in VHDL 2002 or 2008?

Thank you.

Weng

Here is my version for the answer:
type P1_Type array(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0);

alias P1 : P1_Type := R(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0);

It should work on both 2002/2008 VHDL.

Thank you.

Weng

 

On Tuesday, December 4, 2018 at 10:39:48 PM UTC-5, Weng Tianxiang wrote:

On Tuesday, December 4, 2018 at 12:37:54 PM UTC-8, Weng Tianxiang wrote:
Hi,

I have a register array with each register having (pointer & data), now I hope to display each of two parts using 2 different names for easy reading in simulation.

Here is code defining the register array R:
type R_Type is array(0 to R_SIZE) of unsigned(POINTER_BITS + DATA_BITS-1 downto 0);
signal R : R_Type;
alias P1 : it shows R array part of (DATA_BITS-1 downto 0);
alias P2 : it shows R array part of (POINTER_BITS-1 downto DATA_BITS);

How to write the 2 alias statements in VHDL 2002 or 2008?

Thank you.

Weng

Here is my version for the answer:
type P1_Type array(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0);

alias P1 : P1_Type := R(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0);

It should work on both 2002/2008 VHDL.

"Should" work??? Haven't you tested it?

Rick C.

Tesla referral code - https://ts.la/richard11209

 

[Weng Tianxiang]

On Wednesday, December 5, 2018 at 5:37:26 AM UTC-8, gnuarm.del...@gmail.com wrote:

On Tuesday, December 4, 2018 at 10:39:48 PM UTC-5, Weng Tianxiang wrote:
On Tuesday, December 4, 2018 at 12:37:54 PM UTC-8, Weng Tianxiang wrote:
Hi,

I have a register array with each register having (pointer & data), now I hope to display each of two parts using 2 different names for easy reading in simulation.

Here is code defining the register array R:
type R_Type is array(0 to R_SIZE) of unsigned(POINTER_BITS + DATA_BITS-1 downto 0);
signal R : R_Type;
alias P1 : it shows R array part of (DATA_BITS-1 downto 0);
alias P2 : it shows R array part of (POINTER_BITS-1 downto DATA_BITS);

How to write the 2 alias statements in VHDL 2002 or 2008?

Thank you.

Weng

Here is my version for the answer:
type P1_Type array(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0);

alias P1 : P1_Type := R(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0);

It should work on both 2002/2008 VHDL.

"Should" work??? Haven't you tested it?

Rick C.

Tesla referral code - https://ts.la/richard11209

Hi Rick,

You have been the most famous contributor in FPGA and VHDL group for more than 10 years. If you answer, there is a problem.

Here is a correction version:

type P1_Type array(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0);

alias P1 : P1_Type := R(0 to R_SIZE)(DATA_BITS-1 downto 0);

Currently I have no Modelsim working and have no means to test. If you are kind enough, please test it. I think it SHOULD work.

Thank you.

Weng

 

On Wednesday, December 5, 2018 at 11:07:50 AM UTC-5, Weng Tianxiang wrote:

On Wednesday, December 5, 2018 at 5:37:26 AM UTC-8, gnuarm.del...@gmail.com wrote:
On Tuesday, December 4, 2018 at 10:39:48 PM UTC-5, Weng Tianxiang wrote:
On Tuesday, December 4, 2018 at 12:37:54 PM UTC-8, Weng Tianxiang wrote:
Hi,

I have a register array with each register having (pointer & data), now I hope to display each of two parts using 2 different names for easy reading in simulation.

Here is code defining the register array R:
type R_Type is array(0 to R_SIZE) of unsigned(POINTER_BITS + DATA_BITS-1 downto 0);
signal R : R_Type;
alias P1 : it shows R array part of (DATA_BITS-1 downto 0);
alias P2 : it shows R array part of (POINTER_BITS-1 downto DATA_BITS);

How to write the 2 alias statements in VHDL 2002 or 2008?

Thank you.

Weng

Here is my version for the answer:
type P1_Type array(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0);

alias P1 : P1_Type := R(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0);

It should work on both 2002/2008 VHDL.

"Should" work??? Haven't you tested it?

Rick C.

Tesla referral code - https://ts.la/richard11209

Hi Rick,

You have been the most famous contributor in FPGA and VHDL group for more than 10 years. If you answer, there is a problem.

First, don't assume that a "frequent" contributor means someone who knows anything. Then notice I only asked a question. I didn't say there was anything wrong.

Here is a correction version:

type P1_Type array(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0);

alias P1 : P1_Type := R(0 to R_SIZE)(DATA_BITS-1 downto 0);

Currently I have no Modelsim working and have no means to test. If you are kind enough, please test it. I think it SHOULD work.

You can download a copy of nearly any FPGA vendor's tools and use whichever simulator they include. I would run it for you, but I am pretty busy at the moment. I'm with a friend who has gone through surgery and I have business tasks to deal with. Sorry I can't help more.

Rick C.

Tesla referral code + https://ts.la/richard11209