how to write a differentiator in Verilog

[Amir]

Hi,
I would like to write a differentiator in verilog.
the input is a signal (let's call it "valid")
the differentiator will drive one on it's output only in the first
cycle of the valid posedge.

any tips?

thanks in advance
-Amir

 

[gabor]

On Oct 8, 5:23 am, Amir <sting...@gmail.com> wrote:

Hi,
I would like to write a differentiator  in verilog.
the input is a signal (let's call it "valid")
the differentiator will drive one on it's output only in the first
cycle of the valid posedge.

any tips?

thanks in advance
 -Amir

I'm a little confused on your wording. When you say
"first cycle of the valid posedge" are you talking
about a clock cycle (i.e. not the "valid" input) or
the time from the first posedge of "valid" until the
next one? Can you draw a timing diagram of what you
want?

Regards,
Gabor

 

[John_H]

Amir wrote:

Hi,
I would like to write a differentiator in verilog.
the input is a signal (let's call it "valid")
the differentiator will drive one on it's output only in the first
cycle of the valid posedge.

any tips?

thanks in advance
-Amir

If your valid is synchronous, you just need a delay element and a tiny
bit of logic. Look at the truth table or a timing diagram.

reg delay;
always @(posedge clk) delay <= valid;
wire valid_pulse = valid & ~delay;

 

[Amir]

On Oct 8, 4:15 pm, gabor <ga...@alacron.com> wrote:

On Oct 8, 5:23 am, Amir <sting...@gmail.com> wrote:

Hi,
I would like to write a differentiator  in verilog.
the input is a signal (let's call it "valid")
the differentiator will drive one on it's output only in the first
cycle of the valid posedge.

any tips?

thanks in advance
 -Amir

I'm a little confused on your wording.  When you say
"first cycle of the valid posedge" are you talking
about a clock cycle (i.e. not the "valid" input) or
the time from the first posedge of "valid" until the
next one?  Can you draw a timing diagram of what you
want?

Regards,
Gabor

clk ___---___---___---___
valid _________------------
diff_valid _________------______

 

[sandeep]

On Oct 9, 8:13 am, Amir <sting...@gmail.com> wrote:

On Oct 8, 4:15 pm, gabor <ga...@alacron.com> wrote:





On Oct 8, 5:23 am, Amir <sting...@gmail.com> wrote:

Hi,
I would like to write a differentiator  in verilog.
the input is a signal (let's call it "valid")
the differentiator will drive one on it's output only in the first
cycle of the valid posedge.

any tips?

thanks in advance
 -Amir

I'm a little confused on your wording.  When you say
"first cycle of the valid posedge" are you talking
about a clock cycle (i.e. not the "valid" input) or
the time from the first posedge of "valid" until the
next one?  Can you draw a timing diagram of what you
want?

Regards,
Gabor

clk         ___---___---___---___
valid       _________------------
diff_valid  _________------______- Hide quoted text -

- Show quoted text -
John_H has replied it ..and to make it work for both edge last

expression can be relaced with
wire valid_pulse = valid^delay;

regards