How to vary the number and width of ports?

[Steven Alexander]

Hi,

I am relatively new to Verilog and I want to write various cores where
the number of input ports will vary. I know how to very the width of
input ports using the parameter and defparam statements but I can't
seem to vary the number of input ports. Can anyone help?

Steve

 

[Ensoul Chee]

Do you think you can do it in circuit?

"Steven Alexander" <salexander@eee.strath.ac.uk> ????
news:5112460e.0405110821.39a86d58@posting.google.com...

Hi,

I am relatively new to Verilog and I want to write various cores where
the number of input ports will vary. I know how to very the width of
input ports using the parameter and defparam statements but I can't
seem to vary the number of input ports. Can anyone help?

Steve

 

[Allan Herriman]

On Wed, 12 May 2004 11:42:26 +0800, "Ensoul Chee" <mpub@sohu.com>
wrote:

Do you think you can do it in circuit?

Why not? The OP said "using the parameter and defparam statements"
which implies that he wants to have the number of ports fixed at
elaboration.

The obvious solution [that works in other languages] is to have a port
that is an array of vectors, and vary the size of the array with a
parameter.

This can be approximated in Verilog by flattening the array into a
vector.

Regards,
Allan.

 

[Jon Beniston]

salexander@eee.strath.ac.uk (Steven Alexander) wrote in message news:<5112460e.0405110821.39a86d58@posting.google.com>...

Hi,

I am relatively new to Verilog and I want to write various cores where
the number of input ports will vary. I know how to very the width of
input ports using the parameter and defparam statements but I can't
seem to vary the number of input ports. Can anyone help?

Steve

I usually end up using `ifdefs.

i.e.

mod mod (
.clk (clk),
`ifdef SOME_FUNCTIONALITY
.port (wire),
`endif
.other (wires)
);

Cheers,
JonB