How to use VIO and core inserter at the same time.

A

aaron123

Guest
Hi,
I'am seeking a way to use VIO and core inserter at the same time.
found that if I want to use VIO , I must also instantiating ILA. I fee
it's awkward.
Please help me find a better way.Thanks.



---------------------------------------
Posted through http://www.FPGARelated.com
 
Aaron

We recently ran into this ourselves. I think the answer is that you
cannot instantiate a VIO or ILA and then use Core Inserter to add
another ILA.

The problem is the ICON primitive. There is only one per chip and if
you insert an ILA it uses the ICON. There is not another you can use
with your instantiated VIO or ILA.

Please correct me if I am wrong on this.

Pete
 
On Aug 13, 2:12 pm, self <padu...@gmail.com> wrote:
Aaron

We recently ran into this ourselves.  I think the answer is that you
cannot instantiate a VIO or ILA and then use Core Inserter to add
another ILA.

The problem is the ICON primitive. There is only one per chip and if
you insert an ILA it uses the ICON.  There is not another you can use
with your instantiated VIO or ILA.

Please correct me if I am wrong on this.

  Pete
Click to expand...
In FPGA devices with multiple internal BSCAN ports you can have
multiple ICON cores.

Ed McGettigan
--
Xilinx
 
Pete
I agreed with you that the problem come from the ICON primitive. Bu
when I have instantiated a ICON and some VIO in my source files, if th
ngdbuild can detect the unused CONTROL port of the ICON core and presen
them to the user , I think we can use the core inserter. I wonder if I ca
do this based on the current version of ISE.
Aaron

We recently ran into this ourselves. I think the answer is that you
cannot instantiate a VIO or ILA and then use Core Inserter to add
another ILA.

The problem is the ICON primitive. There is only one per chip and if
you insert an ILA it uses the ICON. There is not another you can use
with your instantiated VIO or ILA.

Please correct me if I am wrong on this.

Pete
Click to expand...
---------------------------------------
Posted through http://www.FPGARelated.com
 
On Aug 14, 7:33 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
On Aug 13, 2:12 pm, self <padu...@gmail.com> wrote:

Aaron

We recently ran into this ourselves.  I think the answer is that you
cannot instantiate a VIO or ILA and then use Core Inserter to add
another ILA.

The problem is the ICON primitive. There is only one per chip and if
you insert an ILA it uses the ICON.  There is not another you can use
with your instantiated VIO or ILA.

Please correct me if I am wrong on this.

  Pete

In FPGA devices with multiple internal BSCAN ports you can have
multiple ICON cores.

Ed McGettigan
--
Xilinx
Click to expand...
Ed,

why do you answer if you do not know the answer to what was really
asked?

multiply BSCAN - YES (but was not asked)
multiply ICON pors - YES (but was not asked)

manually inserted VIO at the same time with CORE INSERTE - NO (this
was the question)

Antti
 
On Aug 15, 10:05 pm, Antti <antti.luk...@googlemail.com> wrote:
On Aug 14, 7:33 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:





On Aug 13, 2:12 pm, self <padu...@gmail.com> wrote:

Aaron

We recently ran into this ourselves.  I think the answer is that you
cannot instantiate a VIO or ILA and then use Core Inserter to add
another ILA.

The problem is the ICON primitive. There is only one per chip and if
you insert an ILA it uses the ICON.  There is not another you can use
with your instantiated VIO or ILA.

Please correct me if I am wrong on this.

  Pete

In FPGA devices with multiple internal BSCAN ports you can have
multiple ICON cores.

Ed McGettigan
--
Xilinx

Ed,

why do you answer if you do not know the answer to what was really
asked?

multiply BSCAN - YES (but was not asked)
multiply ICON pors - YES (but was not asked)

manually inserted VIO at the same time with CORE INSERTE - NO (this
was the question)

Antti- Hide quoted text -

- Show quoted text -
Click to expand...
I was replying to a post that was not the OP to correct a
misunderstanding. I'm not sure why this raised your ire.

Ed McGettigan
--
Xilinx Inc.
 
On Aug 16, 8:18 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
On Aug 15, 10:05 pm, Antti <antti.luk...@googlemail.com> wrote:





On Aug 14, 7:33 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:

On Aug 13, 2:12 pm, self <padu...@gmail.com> wrote:

Aaron

We recently ran into this ourselves.  I think the answer is that you
cannot instantiate a VIO or ILA and then use Core Inserter to add
another ILA.

The problem is the ICON primitive. There is only one per chip and if
you insert an ILA it uses the ICON.  There is not another you can use
with your instantiated VIO or ILA.

Please correct me if I am wrong on this.

  Pete

In FPGA devices with multiple internal BSCAN ports you can have
multiple ICON cores.

Ed McGettigan
--
Xilinx

Ed,

why do you answer if you do not know the answer to what was really
asked?

multiply BSCAN - YES (but was not asked)
multiply ICON pors - YES (but was not asked)

manually inserted VIO at the same time with CORE INSERTE - NO (this
was the question)

Antti- Hide quoted text -

- Show quoted text -

I was replying to a post that was not the OP to correct a
misunderstanding.  I'm not sure why this raised your ire.

Ed McGettigan
--
Xilinx Inc.
Click to expand...
Hi

and sorry, sorry, sorry, humble apologies!

It was me not reading previous posts carefully enough

well the issue is not with the FPGA device at all, its even irrelevant
if it has 1 more BSCAN primitives, one ICON can have up to 15
ports that can be used (16th is the ICON own identify slot)

so there is absolutely no technical reasons for not being able
VIO and core inserter, except that the Xilinx software doesn't allow
it.

Antti

PS this maybe a very small excuse for my running of Ed this Monday
morning,
but I am in the painful process of firing an employee.
I possible make more headache over it then he does.

So repeating, to Ed personally: Sorry, Sorry, Sorry, you are the man
who
does help when you can. I had no excuse (except my mood) for the
comment I made.
 
On Aug 13, 6:59 am, "aaron123" <Aaronsmagazine@n_o_s_p_a_m.gmail.com>
wrote:
Hi,
    I'am seeking a way to use VIO and core inserter at the same time. I
found that if I want to use VIO , I must also instantiating ILA. I feel
it's awkward.
Please help me find a better way.Thanks.

---------------------------------------        
Posted throughhttp://www.FPGARelated.com
Click to expand...
While not quite what you want to do, a work around is to put the VIO
and ILA in using the generator flow. Just hook the ILA up to anything
convenient at the top level. Go through place and route, and then
open the design in FPGA editor. Under the tools menu is an entry for
ILA. Select that, and you will get a pop up window that will allow you
to reconnect the ILA to the signals you want. Save the ncd, and take
it through PAR again.

Regards,

John McCaskill
www.FasterTechnology.com
 
Thanks,John. Your idea make things better , though it still need generat
the CDC by hand.
On Aug 13, 6:59=A0am, "aaron123" <Aaronsmagazine@n_o_s_p_a_m.gmail.com
wrote:
Hi,
=A0 =A0 I'am seeking a way to use VIO and core inserter at the sam
time.=
I
found that if I want to use VIO , I must also instantiating ILA. I feel
it's awkward.
Please help me find a better way.Thanks.

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com

While not quite what you want to do, a work around is to put the VIO
and ILA in using the generator flow. Just hook the ILA up to anything
convenient at the top level. Go through place and route, and then
open the design in FPGA editor. Under the tools menu is an entry for
ILA. Select that, and you will get a pop up window that will allow you
to reconnect the ILA to the signals you want. Save the ncd, and take
it through PAR again.

Regards,

John McCaskill
www.FasterTechnology.com
Click to expand...
---------------------------------------
Posted through http://www.FPGARelated.com
 
On Aug 17, 2:57 am, "aaron123"
<Aaronsmagazine@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
Thanks,John. Your idea make things better , though it still need generate
the CDC  by hand.



On Aug 13, 6:59=A0am, "aaron123" <Aaronsmagazine@n_o_s_p_a_m.gmail.com
wrote:
Hi,
=A0 =A0 I'am seeking a way to use VIO and core inserter at the same
time.> > I
found that if I want to use VIO , I must also instantiating ILA. I feel
it's awkward.
Please help me find a better way.Thanks.

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com

While not quite what you want to do, a work around is to put the VIO
and ILA in using the generator flow. Just hook the ILA up to anything
convenient at the top level.  Go through place and route, and then
open the design in FPGA editor. Under the tools menu is an entry for
ILA. Select that, and you will get a pop up window that will allow you
to reconnect the ILA to the signals you want.  Save the ncd, and take
it through PAR again.

Regards,

John McCaskill
www.FasterTechnology.com

---------------------------------------        
Posted throughhttp://www.FPGARelated.com
Click to expand...
On the FPGA Editor ILA tool pop up window, there is a write CDC
button. If after you make your changes, you press that it will write
out a new CDC file for that LIA core for you.

Regards,

John McCaskill
www.FasterTechnology.com
 
Hi,John.
Thanks for the solution. The world look better.
On Aug 17, 2:57=A0am, "aaron123"
Aaronsmagazine@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
Thanks,John. Your idea make things better , though it still nee
generate
the CDC =A0by hand.



On Aug 13, 6:59=3DA0am, "aaron123
Aaronsmagazine@n_o_s_p_a_m.gmail.com=

wrote:
Hi,
=3DA0 =3DA0 I'am seeking a way to use VIO and core inserter at th
sam=
e
time.=3D
I
found that if I want to use VIO , I must also instantiating ILA.
fee=
l
it's awkward.
Please help me find a better way.Thanks.

--------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0
Posted throughhttp://www.FPGARelated.com

While not quite what you want to do, a work around is to put the VIO
and ILA in using the generator flow. Just hook the ILA up to anything
convenient at the top level. =A0Go through place and route, and then
open the design in FPGA editor. Under the tools menu is an entry for
ILA. Select that, and you will get a pop up window that will allow you
to reconnect the ILA to the signals you want. =A0Save the ncd, an
take
it through PAR again.

Regards,

John McCaskill
www.FasterTechnology.com

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com

On the FPGA Editor ILA tool pop up window, there is a write CDC
button. If after you make your changes, you press that it will write
out a new CDC file for that LIA core for you.

Regards,

John McCaskill
www.FasterTechnology.com
Click to expand...
---------------------------------------
Posted through http://www.FPGARelated.com
 
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