How to use VHDL IP in verilog top?

I have some IP in VHDL compiled into ip_XXXlib;

How to use it in verilog top in modelsim?

I have compile the IP into the ip_XXXlib, and compile verilog top to
work library. But when elabrating, it can not file these IP.

How to make elebrating can find these.

Thanks in advance.

 

[Jim Wu]

<mpub@sohu.com> wrote in message
news:1111391154.836640.270190@l41g2000cwc.googlegroups.com...

I have some IP in VHDL compiled into ip_XXXlib;

How to use it in verilog top in modelsim?

I have compile the IP into the ip_XXXlib, and compile verilog top to
work library. But when elabrating, it can not file these IP.

How to make elebrating can find these.

Have you tried using "-L" option?

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips