How to use parameter to express constant in case syntax?

[Yang Luo]

here is an example, 4'd1,how to use parameter to express?
parameter ADDR_W = 4;
parameter DATA_W = 3;
input [ADDR_W-1:0] i_addr ;
reg [DATA_W-1:0] r_width;
always @(posedge i_clk or negedge i_rst_n)
begin
if (!i_rst_n) begin
r_width <= {DATA_W{1'd0}};
end
else if(i_re) begin
case(i_addr)
4'd0: r_width <= 3'd2;
4'd1: r_width <= 3'd3;
....
default: r_width <= {DATA_W{1'd0}};
endcase
end
end

 

[GaborSzakacs]

Yang Luo wrote:

here is an example, 4'd1,how to use parameter to express?
parameter ADDR_W = 4;
parameter DATA_W = 3;
input [ADDR_W-1:0] i_addr ;
reg [DATA_W-1:0] r_width;
always @(posedge i_clk or negedge i_rst_n)
begin
if (!i_rst_n) begin
r_width <= {DATA_W{1'd0}};
end
else if(i_re) begin
case(i_addr)
4'd0: r_width <= 3'd2;
4'd1: r_width <= 3'd3;
....
default: r_width <= {DATA_W{1'd0}};
endcase
end
end

If your synthesizer supports Verilog 2001 syntax, then you
can have sized parameters like:

parameter [ADDR_W-1:0] state_1 = 1;

On the other hand, for most usage including case statements
this is equivalent to:

parameter state_1 = 1;

The only case I can think of where you need the width defined is
when you try to do concatenation like:

assign foo = {3'b0,state_1};

You will probably get some die-hards who say it's really important
for the case statement to have numbers that match the width exactly,
but Verilog is very clear on how variables or constants of different
widths are used in an expression. Furthermore, setting the width
of the constant does not mean that your compiler will actuall check
that the constant fits in the number of bits specified. It is
perfectly legal to write 4'd257 for example. With no width
specification the parameter defaults to type integer (32 bits).

--
Gabor

 

[Yang Luo]

在 2016年3月17日星期四 UTC+8下午7:51:44，Yang Luo写道：

here is an example, 4'd1,how to use parameter to express?
parameter ADDR_W = 4;
parameter DATA_W = 3;
input [ADDR_W-1:0] i_addr ;
reg [DATA_W-1:0] r_width;
always @(posedge i_clk or negedge i_rst_n)
begin
if (!i_rst_n) begin
r_width <= {DATA_W{1'd0}};
end
else if(i_re) begin
case(i_addr)
4'd0: r_width <= 3'd2;
4'd1: r_width <= 3'd3;

it will give a warning if I write like this:
4'd1: r_width <= 3;

...
default: r_width <= {DATA_W{1'd0}};
endcase
end
end