Y
Yang Luo
Guest
I wrote a module as follow:
the complier tells me that the LOG2 function is not right. how should I do?
Do I need include some header file? like `include math.h or sth. else?
module simple_dual_ram #(
parameter SIZE = 10,
parameter LEN = 1024
)
(
input clka,
input ena,
input wea,
input [LOG2(LEN)-1:0] addra,
input [SIZE-1:0] dina,
input clkb,
input enb,
input [LOG2(LEN)-1:0] addrb,
output reg [SIZE-1:0] doutb
);
reg [SIZE-1:0] r_data[LEN-1:0];
reg [LOG2(LEN):0] r_cnt;//LOG2(LEN)+1 LOG2(1024)+1 -> 11; LOG2(1023)+1 -> 10
initial //cannot be synthesis
begin
doutb <= {(SIZE-1){1'b0}};
for(r_cnt=0; r_cnt<LEN; r_cnt=r_cnt+1)
r_data[r_cnt] <= {(SIZE-1){1'b0}};
end
always@(posedge clka)
if(wea&ena)
r_data[addra] <= dina;
always@(posedge clkb)
if(enb)
doutb <= r_data[addrb];
endmodule
the complier tells me that the LOG2 function is not right. how should I do?
Do I need include some header file? like `include math.h or sth. else?
module simple_dual_ram #(
parameter SIZE = 10,
parameter LEN = 1024
)
(
input clka,
input ena,
input wea,
input [LOG2(LEN)-1:0] addra,
input [SIZE-1:0] dina,
input clkb,
input enb,
input [LOG2(LEN)-1:0] addrb,
output reg [SIZE-1:0] doutb
);
reg [SIZE-1:0] r_data[LEN-1:0];
reg [LOG2(LEN):0] r_cnt;//LOG2(LEN)+1 LOG2(1024)+1 -> 11; LOG2(1023)+1 -> 10
initial //cannot be synthesis
begin
doutb <= {(SIZE-1){1'b0}};
for(r_cnt=0; r_cnt<LEN; r_cnt=r_cnt+1)
r_data[r_cnt] <= {(SIZE-1){1'b0}};
end
always@(posedge clka)
if(wea&ena)
r_data[addra] <= dina;
always@(posedge clkb)
if(enb)
doutb <= r_data[addrb];
endmodule