How to use inout ports????

[Jasper]

Hi everybody,

I have to use bidirectional ports in my VHDL design, but it only gives
me problems till so far. In my design I have 2 different blocks.
Because I'm a starter, I will begin simple. In both blocks there is a
counter running on the clock.
In the first one, when the counter runs from 0 to 4, this first block
inout is used as output and the second block is reading this data, so
his inout is used as an input. When both counters are exactly 5, the
inouts of both blocks become 'Z'. From 6 to 10 the direction is the
other way round.
Here is my VHDL code for both blocks, I made a schematic, and linked
the two blocks, clk, rst, and the both inout ports with each other.
After that we runned a functional simulation and the compilation of
this all gave te following error: Does anyone know how to use a
bidirectional port to exchange data between 2 VHDL modules, using
inout?

I hope anyone could help me,

Thanx,

Jasper.

--------------
error
--------------
Logical Error 3509: Output 'N_1' in upper-level source 'bikanten'
can't be redriven to functional_block 'module_2'
Logical Error 3509: Output 'N_1.OE' in upper-level source 'bikanten'
can't be redriven to functional_block 'module_2'

-------------
VHDL CODE
-------------

library ieee;
use ieee.std_logic_1164.all;

entity module_1 is
port(
rst: in std_logic;
clk: in std_logic;
data_1:inout std_logic);

end;

architecture inoutlink of module_1 is
variable count: integer range 0 to 10;
signal int: std_logic;
begin
process (rst, clk)
begin
if rst = '1' then
count := 0;
data_1 <= 'Z';
int <= '0';
elsif rising_edge(clk) then
count := count + 1;
if count < 5 then
data_1 <= '1';
elsif count = 5 then
data_1 <= 'Z';
elsif count > 5 then
int <= data_1;
elsif count = 10 then
count := 0;
end if;
end if;
end process;
end inoutlink;

---------------------------------
second block...
---------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity module_2 is
port(
rst: in std_logic;
clk: in std_logic;
data_1:inout std_logic);

end;

architecture inoutlink of module_2 is

variable count: integer range 0 to 10;
signal int: std_logic;

begin
process (rst, clk)
begin

if rst = '1' then
count := 0;
int <= '0';
data_1 <= 'Z';
elsif rising_edge(clk) then
count := count + 1;
if count < 5 then
int <= data_1;
elsif count = 5 then
data_1 <= 'Z';
elsif count > 5 then
data_1 <= '1';
elsif count = 10 then
count := 0;
end if;
end if;
end process;
end inoutlink;
------------------------------
end
------------------------------