How to use EAB in Altera FPGA?

J

John

Guest
Hi all:
I have the following verilog codes which shift the serial data to parallel
data.But it cost
too much LEs in Altera FPGA.Then I want to make it wokes in EAB.I do not
what to do.Anybody would help me?

reg[31:0] reg_in[7:0],reg_out[7:0];

always @(posedge clk)
begin
if(reset)
cnt8<=0;
else
if(cnt8==7)
begin
cnt8<=0;
reg_out[0]<=reg_in[0];
reg_out[1]<=reg_in[1];
reg_out[2]<=reg_in[2];
reg_out[3]<=reg_in[3];
reg_out[4]<=reg_in[4];
reg_out[5]<=reg_in[5];
reg_out[6]<=reg_in[6];
reg_out[7]<=reg_in[7];
end
else
begin
cnt8<=cnt8+1;
reg_in[0]<=reg_in[1];
reg_in[1]<=reg_in[2];
reg_in[2]<=reg_in[3];
reg_in[3]<=reg_in[4];
reg_in[4]<=reg_in[5];
reg_in[5]<=reg_in[6];
reg_in[6]<=reg_in[7];
reg_in[7]<=data_receive;

end
end
 
John wrote:
Hi all:
I have the following verilog codes which shift the serial data to parallel
data.But it cost
too much LEs in Altera FPGA.Then I want to make it wokes in EAB.I do not
what to do.Anybody would help me?

reg[31:0] reg_in[7:0],reg_out[7:0];

always @(posedge clk)
begin
if(reset)
cnt8<=0;
else
if(cnt8==7)
begin
cnt8<=0;
reg_out[0]<=reg_in[0];
reg_out[1]<=reg_in[1];
reg_out[2]<=reg_in[2];
reg_out[3]<=reg_in[3];
reg_out[4]<=reg_in[4];
reg_out[5]<=reg_in[5];
reg_out[6]<=reg_in[6];
reg_out[7]<=reg_in[7];
end
else
begin
cnt8<=cnt8+1;
reg_in[0]<=reg_in[1];
reg_in[1]<=reg_in[2];
reg_in[2]<=reg_in[3];
reg_in[3]<=reg_in[4];
reg_in[4]<=reg_in[5];
reg_in[5]<=reg_in[6];
reg_in[6]<=reg_in[7];
reg_in[7]<=data_receive;

end
end
Click to expand...
I don't think an EAB will help you much. This code will use one LAB (8
LEs) for the shift register and 3 or 4 more LEs for the counter. The
shift register can fit in an EAB (but not with the counter), so you will
save only one LAB for using an EAB. Why do you think this uses too many
LEs?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F3079B9.9E9AD29C@yahoo.com>...
John wrote:

Hi all:
I have the following verilog codes which shift the serial data to parallel
data.But it cost
too much LEs in Altera FPGA.Then I want to make it wokes in EAB.I do not
what to do.Anybody would help me?

reg[31:0] reg_in[7:0],reg_out[7:0];

always @(posedge clk)
begin
if(reset)
cnt8<=0;
else
if(cnt8==7)
begin
cnt8<=0;
reg_out[0]<=reg_in[0];
reg_out[1]<=reg_in[1];
reg_out[2]<=reg_in[2];
reg_out[3]<=reg_in[3];
reg_out[4]<=reg_in[4];
reg_out[5]<=reg_in[5];
reg_out[6]<=reg_in[6];
reg_out[7]<=reg_in[7];
end
else
begin
cnt8<=cnt8+1;
reg_in[0]<=reg_in[1];
reg_in[1]<=reg_in[2];
reg_in[2]<=reg_in[3];
reg_in[3]<=reg_in[4];
reg_in[4]<=reg_in[5];
reg_in[5]<=reg_in[6];
reg_in[6]<=reg_in[7];
reg_in[7]<=data_receive;

end
end

I don't think an EAB will help you much. This code will use one LAB (8
LEs) for the shift register and 3 or 4 more LEs for the counter. The
shift register can fit in an EAB (but not with the counter), so you will
save only one LAB for using an EAB. Why do you think this uses too many
LEs?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Click to expand...

Question...

Wont you receive valid serial data when cnt8 = 8 ? Your code does not
seem to sample serial data when cnt8 = 8 and just seems to output
parallel data.

- Prasanna
 
rickman <spamgoeshere4@yahoo.com> wrote in message
news:3F3079B9.9E9AD29C@yahoo.com...
I don't think an EAB will help you much. This code will use one LAB (8
LEs) for the shift register and 3 or 4 more LEs for the counter. The
shift register can fit in an EAB (but not with the counter), so you will
save only one LAB for using an EAB. Why do you think this uses too many
LEs?

--
Click to expand...
I guess you overlooked the register definition:

reg[31:0] reg_in[7:0],reg_out[7:0];

Corret me if I am wrong, the code is actually converting an 8 bit wide data
input to a 256 wide data output, so it requires much more than 8 LEs.

Take a look at the link below to see if it helps:
http://www.altera.com/support/software/eda_maxplus2/synplty/intro/logicop.ht
ml

Jim Wu
jimwu88NOOOOOOSPAM@yahoo.com
 
Prasanna wrote:
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F3079B9.9E9AD29C@yahoo.com>...
John wrote:

Hi all:
I have the following verilog codes which shift the serial data to parallel
data.But it cost
too much LEs in Altera FPGA.Then I want to make it wokes in EAB.I do not
what to do.Anybody would help me?

reg[31:0] reg_in[7:0],reg_out[7:0];

always @(posedge clk)
begin
if(reset)
cnt8<=0;
else
if(cnt8==7)
begin
cnt8<=0;
reg_out[0]<=reg_in[0];
reg_out[1]<=reg_in[1];
reg_out[2]<=reg_in[2];
reg_out[3]<=reg_in[3];
reg_out[4]<=reg_in[4];
reg_out[5]<=reg_in[5];
reg_out[6]<=reg_in[6];
reg_out[7]<=reg_in[7];
end
else
begin
cnt8<=cnt8+1;
reg_in[0]<=reg_in[1];
reg_in[1]<=reg_in[2];
reg_in[2]<=reg_in[3];
reg_in[3]<=reg_in[4];
reg_in[4]<=reg_in[5];
reg_in[5]<=reg_in[6];
reg_in[6]<=reg_in[7];
reg_in[7]<=data_receive;

end
end

I don't think an EAB will help you much. This code will use one LAB (8
LEs) for the shift register and 3 or 4 more LEs for the counter. The
shift register can fit in an EAB (but not with the counter), so you will
save only one LAB for using an EAB. Why do you think this uses too many
LEs?

Question...

Wont you receive valid serial data when cnt8 = 8 ? Your code does not
seem to sample serial data when cnt8 = 8 and just seems to output
parallel data.

- Prasanna
Click to expand...
cnt8 will never reaches 8. It counts 0 to 7. But I think you are right
in that reg_in will not shift serial data in on cnt8 = 7. It stops
shifting and so only 7 serial in samples are ever loaded into reg_in
before 8 bits are parallel loaded to reg_out. So reg_out will get 7 new
bits and one old bit. This can be changed so that reg_in gets shifted
outside of the if statement. Then every clock will shift in and reg_out
will get 8 new bits each time.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
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