K
Konx
Guest
Hi everyone.
I'm trying to use a block RAM, generated by Xilinx Core Generator, but
I'm not very expert in Verilog language...
What I want to do is the following:
- create a RAM: the ram has 8192 position (so, 13-bit address) and
every position can store 49 bit (done).
- on one FPGA pin, I have the incoming _serial_ data: at every
falling edge of the clk (and when the TOKEN signal is = 1, or another
control signal is = 1) one data is arriving. The token signal is long
enough to permit the arrivals of 48 bit.
- at the moment I want to store this 48 bit inside an array, then
write in the last bit a 1 and then store this 49-bit array inside the
first address.
- then, token goes to zero, and I wait until the next time TOKEN go
back to 1 to receive again others 48 bits.
So, my final situation should be: 8192 address in the RAM, completely
filled with 49-bit data.
Now, more or less I have the idea of how to do this (basically, "for"
cycle with "if" condition to check the last bit and see if the
position in the RAM is already filled). The problem is to translate
this algorithm in Verilog language.
This is the description of my istantiated block:
memory M1 (
.clka(clk),
.rsta(reset),
.ena(token), //this pin enables write/read/reset operation, probably
is not necessary
.wea(token), // Bus [0:0] - this pin enables write operation
.addra(addra), // Bus [12 : 0]
.dina(out), // Bus[48:0] - The Input pin of the memory is connected
to the out pin of the
// testbench, because this is the pin where the data are
arriving
.douta(douta)); // Bus [48:0]
Then, I set the initial condition:
initial
begin
read_state=1'b0;
reset<=1'b0;
clk<=1'b0;
hit<=1'b0;
token<=1'b0;
trigger<=1'b0;
data [47:0] <=48'b000000000000000000000000000000000000000000000000;
i=0;
hit_counting_mode<=1'b0;
addra [12:0] <=13'b0000000000000;
end
Then, there is the readout part of the code, that at the moment is
something like this:
always@(negedge clk)
begin
if(read_state&&(i<48)&&dina[48]==0)
begin
data<=out;
dina<=out;
i<=i+1;
end
if(read_state&&(i==48)&&dina[48]==0)
begin
dina[48]<=1;
end
if(~read_state)
i<=0;
end
More or less this should work, but what I don't really understand is
how to put the data inside the first address of the RAM, and then
increase the address for the next incomin data.
Do you have any suggestion? I hope the problem is clear enough.
Thank you
Francesco.
I'm trying to use a block RAM, generated by Xilinx Core Generator, but
I'm not very expert in Verilog language...
What I want to do is the following:
- create a RAM: the ram has 8192 position (so, 13-bit address) and
every position can store 49 bit (done).
- on one FPGA pin, I have the incoming _serial_ data: at every
falling edge of the clk (and when the TOKEN signal is = 1, or another
control signal is = 1) one data is arriving. The token signal is long
enough to permit the arrivals of 48 bit.
- at the moment I want to store this 48 bit inside an array, then
write in the last bit a 1 and then store this 49-bit array inside the
first address.
- then, token goes to zero, and I wait until the next time TOKEN go
back to 1 to receive again others 48 bits.
So, my final situation should be: 8192 address in the RAM, completely
filled with 49-bit data.
Now, more or less I have the idea of how to do this (basically, "for"
cycle with "if" condition to check the last bit and see if the
position in the RAM is already filled). The problem is to translate
this algorithm in Verilog language.
This is the description of my istantiated block:
memory M1 (
.clka(clk),
.rsta(reset),
.ena(token), //this pin enables write/read/reset operation, probably
is not necessary
.wea(token), // Bus [0:0] - this pin enables write operation
.addra(addra), // Bus [12 : 0]
.dina(out), // Bus[48:0] - The Input pin of the memory is connected
to the out pin of the
// testbench, because this is the pin where the data are
arriving
.douta(douta)); // Bus [48:0]
Then, I set the initial condition:
initial
begin
read_state=1'b0;
reset<=1'b0;
clk<=1'b0;
hit<=1'b0;
token<=1'b0;
trigger<=1'b0;
data [47:0] <=48'b000000000000000000000000000000000000000000000000;
i=0;
hit_counting_mode<=1'b0;
addra [12:0] <=13'b0000000000000;
end
Then, there is the readout part of the code, that at the moment is
something like this:
always@(negedge clk)
begin
if(read_state&&(i<48)&&dina[48]==0)
begin
data<=out;
dina<=out;
i<=i+1;
end
if(read_state&&(i==48)&&dina[48]==0)
begin
dina[48]<=1;
end
if(~read_state)
i<=0;
end
More or less this should work, but what I don't really understand is
how to put the data inside the first address of the RAM, and then
increase the address for the next incomin data.
Do you have any suggestion? I hope the problem is clear enough.
Thank you
Francesco.