I
iceman
Guest
anyone have a schematic how to use 74hc74... i cant make it work...tnx
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R
Robert Monsen
Guest
iceman wrote:
/Reset1 -1| |o- Vcc
Data1 -o| |o- /Reset2
Clock1 -o| |o- Data2
/Set1 -o| |o- Clock2
Q1 -o| |o- /Set2
/Q1 -o| |o- Q2
GND -o|__|o- /Q2
(created by AACircuit v1.28 beta 10/06/04 www.tech-chat.de)
Make sure the /Set and /Reset lines are high, unless you want to reset
or set the thing.
Power Vcc at 5V, ground at 0V.
Set the Clock to 0V. Set the Data input to some value, then make the
Clock go to 5V, then back to 0V. Now, the value that was on the Data pin
is on the Q pin, even if the Data pin subsequently changes. The /Q pin
(almost) always gives the complement of the Q pin (See below).
There are two devices per chip, as can be seen above.
There are requirements relating to setup and hold times for the data and
clock pins. If you don't have the data set for a period of time before
asserting the clock, the data not get latched onto the output. This
setup time is normally something under 10ns, depending on your logic family.
/Set = 0 will make the Q output high, regardless of what was there
before. /Reset - 0 will make the Q output low, regardless of what was
there before. Making both /Set and /Reset low at the same time will
result in both Q and /Q going high (Thus, not being complements of each
other).
Make sure the signal is fast and clean for the clock. Slow clocks can
cause multiple transtions, which are confusing when you are feeding the
/Q output back to the Data input. If the clock is dirty, a schmitt
trigger will clean it up.
--
Regards,
Robert Monsen
"Your Highness, I have no need of this hypothesis."
- Pierre Laplace (1749-1827), to Napoleon,
on why his works on celestial mechanics make no mention of God.
__anyone have a schematic how to use 74hc74... i cant make it work...tnx
/Reset1 -1| |o- Vcc
Data1 -o| |o- /Reset2
Clock1 -o| |o- Data2
/Set1 -o| |o- Clock2
Q1 -o| |o- /Set2
/Q1 -o| |o- Q2
GND -o|__|o- /Q2
(created by AACircuit v1.28 beta 10/06/04 www.tech-chat.de)
Make sure the /Set and /Reset lines are high, unless you want to reset
or set the thing.
Power Vcc at 5V, ground at 0V.
Set the Clock to 0V. Set the Data input to some value, then make the
Clock go to 5V, then back to 0V. Now, the value that was on the Data pin
is on the Q pin, even if the Data pin subsequently changes. The /Q pin
(almost) always gives the complement of the Q pin (See below).
There are two devices per chip, as can be seen above.
There are requirements relating to setup and hold times for the data and
clock pins. If you don't have the data set for a period of time before
asserting the clock, the data not get latched onto the output. This
setup time is normally something under 10ns, depending on your logic family.
/Set = 0 will make the Q output high, regardless of what was there
before. /Reset - 0 will make the Q output low, regardless of what was
there before. Making both /Set and /Reset low at the same time will
result in both Q and /Q going high (Thus, not being complements of each
other).
Make sure the signal is fast and clean for the clock. Slow clocks can
cause multiple transtions, which are confusing when you are feeding the
/Q output back to the Data input. If the clock is dirty, a schmitt
trigger will clean it up.
--
Regards,
Robert Monsen
"Your Highness, I have no need of this hypothesis."
- Pierre Laplace (1749-1827), to Napoleon,
on why his works on celestial mechanics make no mention of God.