A
anon
Guest
I am looking for a way to implement a bus width converter. input is x bits while the output is 2x. both sides run at the clock frequency. any ideas?
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I am looking for a way to implement a bus width converter. input is x
bits while the output is 2x. both sides run at the clock frequency. any ideas?
In article <76b9fdd8-043b-4817-b5c4-cccf5a6d4720@googlegroups.com>,
anon <vadlmans@gmail.com> wrote:
I am looking for a way to implement a bus width converter. input is x
bits while the output is 2x. both sides run at the clock frequency. any ideas?
Well, to stuff zeros onto the bus (MSBs):
wire [ 2 * BUS_WIDTH - 1 : 0 ] outbus = inbus;
To replicated the LSB to the MSBs
wire [ 2 * BUS_WIDTH - 1 : 0 ] = { 2 { inbus } };
To create a stack (it depends on your handshaking):
reg [ 2 * BUS_WIDTH - 1 : 0 ] outbus;
always @( posedge clk )
outbus <= { outbus, inbus };
reg outbus_valid;
always @( posedge clk )
outbus_valid <= ~outbus_valid; // outbus is valid every other input cycle
A lot depends on you're actual spec requirements, bus protocols, etc.
Those are basic ideas. Without more details on what you're actually
looking for, it's hard to make suggestions.
Regards,
Mark