How to think with Systemverilog interfaces

Guest
Hi!
I need the wisdom of the group since I'm quite new to SV.

Let's say that I have 4 modules A,B,C,D that should be connected
together.

Each module has it's own interface A_IF, B_IF,C_IF, D_IF.

Now on the top level I want to connect some signals from A to some
signals in B and some signals in C.


So I would instantiate the modules and the interfaces:
A_IF A_IF_PINS()
B_IF B_IF_PINS()
C_IF C_IF_PINS()
D_IF D_IF_PINS()

A A_INST(....
B B_INST(...
C C_INST(...
D D_INST(...

So let's say that I want the signal RQST in interface A connected to
the signal REQUEST in interface B. How do I do that?


And if I would design the whole lot from the beginning, should I have
ONE interface/module:
module A( interface pins);
or have ONE interface/ "logical interface", e.g.
module A( interface A2B, interface A2C, interface A2D);

I know, there's more than one way to do it, but I need to figure out
the best way to think. The examples in various documentation only talk
about communication between two modules.

/Mikael
 
Hi Mikael,

(Please read interfaces with modports from any SV book or SV LRM)

If I understood your problem correctly then I would solve your problem
this way....

Create an interface with four modports which will define port list of
each module A, B, C and D. In top level you can instantiate this
interface and appropraitely you can connect all the modules together
with interface instance.

interface Intf;

modport modA (...);
modport modB (...);
modport modC (...);
modport modD (...);
endinterface

module A (Intf.modA I);
endmodule

module B (Intf.modB I);
endmodule

module C (Intf.modC I);
endmodule

module D (Intf.modD I);
endmodule

module top;
Intf I();
A U1(I);
B U2(I);
C U3(I);
D U4(I);
endmodule

- Mukesh Chauhan

mickedykare@yahoo.se wrote:
Hi!
I need the wisdom of the group since I'm quite new to SV.

Let's say that I have 4 modules A,B,C,D that should be connected
together.

Each module has it's own interface A_IF, B_IF,C_IF, D_IF.

Now on the top level I want to connect some signals from A to some
signals in B and some signals in C.


So I would instantiate the modules and the interfaces:
A_IF A_IF_PINS()
B_IF B_IF_PINS()
C_IF C_IF_PINS()
D_IF D_IF_PINS()

A A_INST(....
B B_INST(...
C C_INST(...
D D_INST(...

So let's say that I want the signal RQST in interface A connected to
the signal REQUEST in interface B. How do I do that?


And if I would design the whole lot from the beginning, should I have
ONE interface/module:
module A( interface pins);
or hae ONE interface/ "logical interface", e.g.
module A( interface A2B, interface A2C, interface A2D);

I know, there's more than one way to do it, but I need to figure out
the best way to think. The examples in various documentation only talk
about communication between two modules.

/Mikael
Click to expand...
 
module top;
Intf I();
A U1(I);
B U2(I);
C U3(I);
D U4(I);
endmodule
Click to expand...
You mean
module top;
Intf I();
A U1(I.modA);
B U2(I.modB);
C U3(I.modC);
D U4(I.modD);
endmodule


Muks escreveu:

Hi Mikael,

(Please read interfaces with modports from any SV book or SV LRM)

If I understood your problem correctly then I would solve your problem
this way....

Create an interface with four modports which will define port list of
each module A, B, C and D. In top level you can instantiate this
interface and appropraitely you can connect all the modules together
with interface instance.

interface Intf;

modport modA (...);
modport modB (...);
modport modC (...);
modport modD (...);
endinterface

module A (Intf.modA I);
endmodule

module B (Intf.modB I);
endmodule

module C (Intf.modC I);
endmodule

module D (Intf.modD I);
endmodule

module top;
Intf I();
A U1(I);
B U2(I);
C U3(I);
D U4(I);
endmodule

- Mukesh Chauhan

mickedykare@yahoo.se wrote:
Hi!
I need the wisdom of the group since I'm quite new to SV.

Let's say that I have 4 modules A,B,C,D that should be connected
together.

Each module has it's own interface A_IF, B_IF,C_IF, D_IF.

Now on the top level I want to connect some signals from A to some
signals in B and some signals in C.


So I would instantiate the modules and the interfaces:
A_IF A_IF_PINS()
B_IF B_IF_PINS()
C_IF C_IF_PINS()
D_IF D_IF_PINS()

A A_INST(....
B B_INST(...
C C_INST(...
D D_INST(...

So let's say that I want the signal RQST in interface A connected to
the signal REQUEST in interface B. How do I do that?


And if I would design the whole lot from the beginning, should I have
ONE interface/module:
module A( interface pins);
or hae ONE interface/ "logical interface", e.g.
module A( interface A2B, interface A2C, interface A2D);

I know, there's more than one way to do it, but I need to figure out
the best way to think. The examples in various documentation only talk
about communication between two modules.

/Mikael
Click to expand...
 
Both will work because I have declared module port list using modports
and not the whole interface is used.
So what I suggested in top module will also work same as what you
written.

- Mukesh

ankitks@yahoo.com wrote:
module top;
Intf I();
A U1(I);
B U2(I);
C U3(I);
D U4(I);
endmodule

You mean
module top;
Intf I();
A U1(I.modA);
B U2(I.modB);
C U3(I.modC);
D U4(I.modD);
endmodule


Muks escreveu:

Hi Mikael,

(Please read interfaces with modports from any SV book or SV LRM)

If I understood your problem correctly then I would solve your problem
this way....

Create an interface with four modports which will define port list of
each module A, B, C and D. In top level you can instantiate this
interface and appropraitely you can connect all the modules together
with interface instance.

interface Intf;

modport modA (...);
modport modB (...);
modport modC (...);
modport modD (...);
endinterface

module A (Intf.modA I);
endmodule

module B (Intf.modB I);
endmodule

module C (Intf.modC I);
endmodule

module D (Intf.modD I);
endmodule

module top;
Intf I();
A U1(I);
B U2(I);
C U3(I);
D U4(I);
endmodule

- Mukesh Chauhan

mickedykare@yahoo.se wrote:
Hi!
I need the wisdom of the group since I'm quite new to SV.

Let's say that I have 4 modules A,B,C,D that should be connected
together.

Each module has it's own interface A_IF, B_IF,C_IF, D_IF.

Now on the top level I want to connect some signals from A to some
signals in B and some signals in C.


So I would instantiate the modules and the interfaces:
A_IF A_IF_PINS()
B_IF B_IF_PINS()
C_IF C_IF_PINS()
D_IF D_IF_PINS()

A A_INST(....
B B_INST(...
C C_INST(...
D D_INST(...

So let's say that I want the signal RQST in interface A connected to
the signal REQUEST in interface B. How do I do that?


And if I would design the whole lot from the beginning, should I have
ONE interface/module:
module A( interface pins);
or hae ONE interface/ "logical interface", e.g.
module A( interface A2B, interface A2C, interface A2D);

I know, there's more than one way to do it, but I need to figure out
the best way to think. The examples in various documentation only talk
about communication between two modules.

/Mikael
Click to expand...
 
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