how to test benching a bidircetional port?

[jtj]

Hi All

I would like to test a bi-directional port in a test bench.
To generate the test bench I use Bencher, a GUI tool that is bundled with
Xilinx ISE.
Assigning OUTDATA to PADPIN works fine but when I try to assign a value to
PADPIN form the test bench
Modelsim gives the following error: "Nonresolved signal padpin has multiple
sources."

What is the trick? -Any help is appreciated since I'm starting to be
frustrated.

Thanks in advance
-Jan


-------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity BIPAD is port (
PADPIN : inout std_ulogic_vector(15 downto 0);
RD : in std_ulogic;
WR : in std_ulogic;
OUTDATA : in std_ulogic_vector(15 downto 0);
INDATA : out std_ulogic_vector(15 downto 0));
end BIPAD;

architecture test of BIPAD is

begin
PADPIN <= OUTDATA when (WR = '1' and RD = '0') else "ZZZZZZZZZZZZZZZZ";
-- PADPIN <= OUTDATA when (WR = '1' and RD = '0'); --else
"ZZZZZZZZZZZZZZZZZZZZZZZZ";
INDATA <= PADPIN when (WR = '0' and RD = '1');
end test;

 

[Allan Herriman]

On Thu, 2 Oct 2003 15:56:10 +0200, "jtj"
<spam_account@business.tele.dk> wrote:

Hi All

I would like to test a bi-directional port in a test bench.
To generate the test bench I use Bencher, a GUI tool that is bundled with
Xilinx ISE.
Assigning OUTDATA to PADPIN works fine but when I try to assign a value to
PADPIN form the test bench
Modelsim gives the following error: "Nonresolved signal padpin has multiple
sources."

What is the trick? -Any help is appreciated since I'm starting to be
frustrated.

Change that signal from std_ulogic(_vector) to std_logic(_vector).
This will make it a resolved signal, which matches what you are trying
to do.
BTW, The 'u' in std_ulogic stands for 'unresolved'.

Allan.