How to tell what is synthesizable and what is not?

[Mahurshi Akilla]

How can we tell what is synthesizable and and what is not in a piece of
verilog code?

(Of course, I guess the synthesizer would complain an die, but for
those of us who only have a free simulator at home, how can we tell
what is not synthesizable?)

Mahurshi Akilla

 

[Jerome]

Hi,

One way is to use the ifdef statement:

`ifdef ReadUnsynthCode
..
..
..
`endif

you just have to define it for the simulation.

Jerome.

Mahurshi Akilla a écrit :

How can we tell what is synthesizable and and what is not in a piece of
verilog code?

(Of course, I guess the synthesizer would complain an die, but for
those of us who only have a free simulator at home, how can we tell
what is not synthesizable?)

Mahurshi Akilla

 

[m]

On 1 Mar 2006 07:04:58 -0800, "Mahurshi Akilla" <mahurshi@gmail.com>
wrote:

How can we tell what is synthesizable and and what is not in a piece of
verilog code?

(Of course, I guess the synthesizer would complain an die, but for
those of us who only have a free simulator at home, how can we tell
what is not synthesizable?)
You can buy the standard or look at this draft:

http://www.eda.org/vlog-synth/vlogrtl.pdf

Also most fpga companies have free development tools which include a
synthesis tool. You can use them as a generic front-end.

 

[selva kumar]

hi,

you can refer following books,
1. verilog synthesis primer by BHASAKAR
2.HDL chip design DOUGHLAS SMITH.

REGARDS
selva
bangalore

Mahurshi Akilla wrote:

How can we tell what is synthesizable and and what is not in a piece of
verilog code?

(Of course, I guess the synthesizer would complain an die, but for
those of us who only have a free simulator at home, how can we tell
what is not synthesizable?)

Mahurshi Akilla