How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA conne

P

Pratap

Guest
Hi,
I want to delay a signal precisely by taking out the signal from the
FPGA so that it can be fed to another chip which can control the delay
through that. I want to feed this delayed signal back to the FPGA by
inputting that signal through another pin on the Xilinx Virtex II Pro
board. I am using the EXT_CLK_P and EXT_CLK_N pins for inputting the
desired signals. The signal to be delayed is fed to the pin EXT_CLK_P
by installing SMA connectors at those points. I have also installed
separate connectors at EXT_CLK_N, MGT_TXP and MGT_TXN. But I am not
able to route the signals as I get the following error while mapping.

Using target part "2vp30ff896-7".
Mapping design into LUTs...
Running directed packing...
ERROR:pack:1107 - Unable to combine the following symbols into a
single IOB
component:
BUF symbol "inp_for_TI_chip_OBUF" (Output Signal =
inp_for_TI_chip)
PAD symbol "inp_for_TI_chip" (Pad Signal = inp_for_TI_chip)
Each of the following constraints specifies an illegal physical
site for a
component of type IOB:
Symbol "inp_for_TI_chip" (LOC=A6)
Please correct the constraints accordingly.

The motivation behind using the SMA connectors for the connectivity is
to have good signal shape of the input square wave signals, by which
the delays can be precisely maintained. I have also tried connect the
output from the FPGA pin for the external delay controller and also
the input signal from the controller to the chip through other Non-SMA
type pins in J5 or J6 connectors. But even doing that doesn't solve my
purpose, as I don't get any thing signal reaching at those points.
Surprisingly, only when I connect those signals intended to be fed to
the external delay controller chip to the externally non-available
pins MGT_CLK_P and MGT_CLK_N, I get all the signals toggling, but my
purpose of routing the signals through the external chip is not
solved.
Can anybody help me understand, why this connection to MGT_CLK_P and
MGT_CLK_N for the stuff to work and how those are hooked upto the
system? How can I solve my purpose of taking the signals fed to
EXT_CLK_P and EXT_CLK_N SMA connectors from the Virtex II Pro board
and route it through another chip.
Looking forward to some helpful suggestions,
Thanks in advance,
Pratap
 
On Mar 25, 5:59 pm, Pratap <pratap.i...@gmail.com> wrote:
Hi,
I want to delay a signal precisely by taking out the signal from the
FPGA so that it can be fed to another chip which can control the delay
through that. I want to feed this delayed signal back to the FPGA by
inputting that signal through another pin on the Xilinx Virtex II Pro
board. I am using the EXT_CLK_P and EXT_CLK_N pins for inputting the
desired signals. The signal to be delayed is fed to the pin EXT_CLK_P
by installing SMA connectors at those points. I have also installed
separate connectors at EXT_CLK_N, MGT_TXP and MGT_TXN. But I am not
able to route the signals as I get the following error while mapping.

Using target part "2vp30ff896-7".
Mapping design into LUTs...
Running directed packing...
ERROR:pack:1107 - Unable to combine the following symbols into a
single IOB
   component:
        BUF symbol "inp_for_TI_chip_OBUF" (Output Signal > inp_for_TI_chip)
        PAD symbol "inp_for_TI_chip" (Pad Signal = inp_for_TI_chip)
   Each of the following constraints specifies an illegal physical
site for a
   component of type IOB:
        Symbol "inp_for_TI_chip" (LOC=A6)
   Please correct the constraints accordingly.

The motivation behind using the SMA connectors for the connectivity is
to have good signal shape of the input square wave signals, by which
the delays can be precisely maintained. I have also tried connect the
output from the FPGA pin for the external delay controller and also
the input signal from the controller to the chip through other Non-SMA
type pins in J5 or J6 connectors. But even doing that doesn't solve my
purpose, as I don't get any thing signal reaching at those points.
Surprisingly, only when I connect those signals intended to be fed to
the external delay controller chip to the externally non-available
pins MGT_CLK_P and MGT_CLK_N, I get all the signals toggling, but my
purpose of routing the signals through the external chip is not
solved.
Can anybody help me understand, why this connection to MGT_CLK_P and
MGT_CLK_N for the stuff to work and how those are hooked upto the
system? How can I solve my purpose of taking the signals fed to
EXT_CLK_P and EXT_CLK_N SMA connectors from the Virtex II Pro board
and route it through another chip.
Looking forward to some helpful suggestions,
Thanks in advance,
Pratap
Click to expand...
The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be used
by the MGTs. In the Virtex-II Pro FPGA family the MGT reference clock
pins were normal I/Os that had extra dedicated routing to the MGTs.

Are you using a Xilinx board? If so which one is it?

What are the IO location constraints that you are using for the output
and input paths?

Ed McGettigan
--
Xilinx Inc.
 
The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be used
by the MGTs.  In the Virtex-II Pro FPGA family the MGT reference clock
pins were normal I/Os that had extra dedicated routing to the MGTs.

Are you using a Xilinx board?  If so which one is it?

What are the IO location constraints that you are using for the output
and input paths?

Ed McGettigan
--
Xilinx Inc.
Click to expand...
Hello,
I am using the Virtex II Pro development board for my project.
I am pasting all the IO constraints written to the ucf file.
The signals to take out and then feed in are "inp_for_TI_chip" and
"op_from_TI_chip" respectively.

NET "reset_in" LOC = "AH1" | IOSTANDARD = LVCMOS25;
#LEFT P/B

NET "clk_in" LOC = "G15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_P

NET "samp_clk" LOC = "F15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_N

NET "op_from_TI_chip" LOC = "A6" | IOSTANDARD = LVCMOS25;
#MGT_TXP

NET "inp_for_TI_chip" LOC = "A7" | IOSTANDARD = LVCMOS25 | SLEW FAST | DRIVE = 8 ;
#MGT_TXN

NET "ti_delay_chip_cntl" LOC = "R9" | IOSTANDARD = LVCMOS25 | SLEW FAST | DRIVE = 8 ;
#J5-11

NET "dir_fine_delay" LOC = "P1" | IOSTANDARD = LVCMOS25 | SLEW = FAST
| DRIVE = 8 ;
#J5-15

NET "board_in1" LOC = "AB1" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-27

NET "board_in2" LOC = "W8" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-35

NET "cleaned_clk1" LOC = "R3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-31

NET "cleaned_clk2" LOC = "U3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-39

NET "status(3)" LOC = "AC4" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(2)" LOC = "AC3" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(1)" LOC = "AA6" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(0)" LOC = "AA5" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;


Thanks,
Pratap
 
On Mar 26, 7:53 am, Pratap <pratap.i...@gmail.com> wrote:
The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be used
by the MGTs.  In the Virtex-II Pro FPGA family the MGT reference clock
pins were normal I/Os that had extra dedicated routing to the MGTs.

Are you using a Xilinx board?  If so which one is it?

What are the IO location constraints that you are using for the output
and input paths?

Ed McGettigan
--
Xilinx Inc.

Hello,
I am using the Virtex II Pro development board for my project.
I am pasting all the IO constraints written to the ucf file.
The signals to take out and then feed in are "inp_for_TI_chip" and
"op_from_TI_chip" respectively.

NET "reset_in" LOC = "AH1" | IOSTANDARD = LVCMOS25;
#LEFT P/B

NET "clk_in" LOC = "G15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_P

NET "samp_clk" LOC = "F15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_N

NET "op_from_TI_chip"  LOC = "A6" | IOSTANDARD = LVCMOS25;
#MGT_TXP

NET "inp_for_TI_chip"  LOC = "A7" | IOSTANDARD = LVCMOS25 | SLEW > FAST | DRIVE = 8 ;
#MGT_TXN

NET "ti_delay_chip_cntl"  LOC = "R9" | IOSTANDARD = LVCMOS25 | SLEW > FAST | DRIVE = 8 ;
#J5-11

NET "dir_fine_delay"  LOC = "P1" | IOSTANDARD = LVCMOS25 | SLEW = FAST
| DRIVE = 8 ;
#J5-15

NET "board_in1"  LOC = "AB1" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-27

NET "board_in2"  LOC = "W8" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-35

NET "cleaned_clk1"  LOC = "R3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-31

NET "cleaned_clk2"  LOC = "U3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-39

NET "status(3)" LOC = "AC4" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(2)" LOC = "AC3" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(1)" LOC = "AA6" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(0)" LOC = "AA5" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;

Thanks,
Pratap

I am using the Virtex II Pro development board for my project.
Click to expand...
This is about as useful as saying that your computer has an Intel ATX
motherboard. Who made the board, and what is the model number?

Ed McGettigan
--
Xilinx Inc.
 
On Mar 26, 7:53 am, Pratap <pratap.i...@gmail.com> wrote:
The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be used
by the MGTs.  In the Virtex-II Pro FPGA family the MGT reference clock
pins were normal I/Os that had extra dedicated routing to the MGTs.

Are you using a Xilinx board?  If so which one is it?

What are the IO location constraints that you are using for the output
and input paths?

Ed McGettigan
--
Xilinx Inc.

Hello,
I am using the Virtex II Pro development board for my project.
I am pasting all the IO constraints written to the ucf file.
The signals to take out and then feed in are "inp_for_TI_chip" and
"op_from_TI_chip" respectively.

NET "reset_in" LOC = "AH1" | IOSTANDARD = LVCMOS25;
#LEFT P/B

NET "clk_in" LOC = "G15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_P

NET "samp_clk" LOC = "F15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_N

NET "op_from_TI_chip"  LOC = "A6" | IOSTANDARD = LVCMOS25;
#MGT_TXP

NET "inp_for_TI_chip"  LOC = "A7" | IOSTANDARD = LVCMOS25 | SLEW > FAST | DRIVE = 8 ;
#MGT_TXN

NET "ti_delay_chip_cntl"  LOC = "R9" | IOSTANDARD = LVCMOS25 | SLEW > FAST | DRIVE = 8 ;
#J5-11

NET "dir_fine_delay"  LOC = "P1" | IOSTANDARD = LVCMOS25 | SLEW = FAST
| DRIVE = 8 ;
#J5-15

NET "board_in1"  LOC = "AB1" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-27

NET "board_in2"  LOC = "W8" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-35

NET "cleaned_clk1"  LOC = "R3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-31

NET "cleaned_clk2"  LOC = "U3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-39

NET "status(3)" LOC = "AC4" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(2)" LOC = "AC3" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(1)" LOC = "AA6" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(0)" LOC = "AA5" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;

Thanks,
Pratap
Click to expand...
The UCF file constraints have regular IO location assignments to A7
and A6 which are the MGT TXP/TXN pins. These locations are not valid
for anything other than MGT TXP/TXN pins and your original post
indicated that you had changed these to other locations and it worked.

I'm confused. What exactly is your question or problem?

Ed McGettigan
--
Xilinx Inc.
 
On Mar 27, 6:39 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
On Mar 26, 7:53 am, Pratap <pratap.i...@gmail.com> wrote:



The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be used
by the MGTs.  In the Virtex-II Pro FPGA family the MGT reference clock
pins were normal I/Os that had extra dedicated routing to the MGTs.

Are you using a Xilinx board?  If so which one is it?

What are the IO location constraints that you are using for the output
and input paths?

Ed McGettigan
--
Xilinx Inc.

Hello,
I am using the Virtex II Pro development board for my project.
I am pasting all the IO constraints written to the ucf file.
The signals to take out and then feed in are "inp_for_TI_chip" and
"op_from_TI_chip" respectively.

NET "reset_in" LOC = "AH1" | IOSTANDARD = LVCMOS25;
#LEFT P/B

NET "clk_in" LOC = "G15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_P

NET "samp_clk" LOC = "F15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_N

NET "op_from_TI_chip"  LOC = "A6" | IOSTANDARD = LVCMOS25;
#MGT_TXP

NET "inp_for_TI_chip"  LOC = "A7" | IOSTANDARD = LVCMOS25 | SLEW > > FAST | DRIVE = 8 ;
#MGT_TXN

NET "ti_delay_chip_cntl"  LOC = "R9" | IOSTANDARD = LVCMOS25 | SLEW > > FAST | DRIVE = 8 ;
#J5-11

NET "dir_fine_delay"  LOC = "P1" | IOSTANDARD = LVCMOS25 | SLEW = FAST
| DRIVE = 8 ;
#J5-15

NET "board_in1"  LOC = "AB1" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-27

NET "board_in2"  LOC = "W8" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-35

NET "cleaned_clk1"  LOC = "R3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-31

NET "cleaned_clk2"  LOC = "U3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-39

NET "status(3)" LOC = "AC4" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(2)" LOC = "AC3" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(1)" LOC = "AA6" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(0)" LOC = "AA5" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;

Thanks,
Pratap

The UCF file constraints have regular IO location assignments to A7
and A6 which are the MGT TXP/TXN pins.  These locations are not valid
for anything other than MGT TXP/TXN pins and your original post
indicated that you had changed these to other locations and it worked.

I'm confused.  What exactly is your question or problem?

Ed McGettigan
--
Xilinx Inc.
Click to expand...

Yes,
This is the ucf file that is not working. The ucf file that ensures
that there is toggling at all the signal ports is as follows.

NET "op_from_TI_chip" LOC = "F16" | IOSTANDARD = LVCMOS25;
#MGT_CLK_P

NET "inp_for_TI_chip" LOC = "G16" | IOSTANDARD = LVCMOS25 | SLEW FAST | DRIVE = 8 ;
#MGT_CLK_N

My exact problem is in understanding why in the case when I connect
the pins intended to be interfaced with the other chip to F16 and
G16(The externally non-accessible ports on board) , I get the signals
at the output port. If I connect those two signals to any other pin,
it doesn't seem to work.
I hope the problem is clear now.

Thanks,
Pratap
 
On Mar 26, 8:41 pm, Pratap <pratap.i...@gmail.com> wrote:
On Mar 27, 6:39 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:





On Mar 26, 7:53 am, Pratap <pratap.i...@gmail.com> wrote:

The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be used
by the MGTs.  In the Virtex-II Pro FPGA family the MGT reference clock
pins were normal I/Os that had extra dedicated routing to the MGTs.

Are you using a Xilinx board?  If so which one is it?

What are the IO location constraints that you are using for the output
and input paths?

Ed McGettigan
--
Xilinx Inc.

Hello,
I am using the Virtex II Pro development board for my project.
I am pasting all the IO constraints written to the ucf file.
The signals to take out and then feed in are "inp_for_TI_chip" and
"op_from_TI_chip" respectively.

NET "reset_in" LOC = "AH1" | IOSTANDARD = LVCMOS25;
#LEFT P/B

NET "clk_in" LOC = "G15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_P

NET "samp_clk" LOC = "F15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_N

NET "op_from_TI_chip"  LOC = "A6" | IOSTANDARD = LVCMOS25;
#MGT_TXP

NET "inp_for_TI_chip"  LOC = "A7" | IOSTANDARD = LVCMOS25 | SLEW > > > FAST | DRIVE = 8 ;
#MGT_TXN

NET "ti_delay_chip_cntl"  LOC = "R9" | IOSTANDARD = LVCMOS25 | SLEW > > > FAST | DRIVE = 8 ;
#J5-11

NET "dir_fine_delay"  LOC = "P1" | IOSTANDARD = LVCMOS25 | SLEW = FAST
| DRIVE = 8 ;
#J5-15

NET "board_in1"  LOC = "AB1" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-27

NET "board_in2"  LOC = "W8" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-35

NET "cleaned_clk1"  LOC = "R3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-31

NET "cleaned_clk2"  LOC = "U3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-39

NET "status(3)" LOC = "AC4" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(2)" LOC = "AC3" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(1)" LOC = "AA6" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(0)" LOC = "AA5" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;

Thanks,
Pratap

The UCF file constraints have regular IO location assignments to A7
and A6 which are the MGT TXP/TXN pins.  These locations are not valid
for anything other than MGT TXP/TXN pins and your original post
indicated that you had changed these to other locations and it worked.

I'm confused.  What exactly is your question or problem?

Ed McGettigan
--
Xilinx Inc.

Yes,
This is the ucf file that is not working. The ucf file that ensures
that there is toggling at all the signal ports is as follows.

NET "op_from_TI_chip"  LOC = "F16" | IOSTANDARD = LVCMOS25;
#MGT_CLK_P

NET "inp_for_TI_chip"  LOC = "G16" | IOSTANDARD = LVCMOS25 | SLEW > FAST | DRIVE = 8 ;
#MGT_CLK_N

My exact problem is in understanding why in the case when I connect
the pins intended to be interfaced with the other chip to F16 and
G16(The externally non-accessible ports on board) , I get the signals
at the output port. If I connect those two signals to any other  pin,
it doesn't seem to work.
I hope the problem is clear now.

Thanks,
Pratap- Hide quoted text -

- Show quoted text -
Click to expand...
Sorry, it still isn't very clear and you still haven't identified
which exact board you are using (vendor and model).

As I said twice already, the MGT TXP/TXN pins A6/A7 cannot be used for
anything other that the MGT. For this device pins F16 and G16 are
regular IO and also MGT reference clock input pins so they can be used
for inputs or outputs.

If I connect those two signals to any other pin,
it doesn't seem to work.
Click to expand...
It isn't clear what you mean by any other pin and what doesn't work.

Ed McGettigan
--
Xilinx Inc.
 
On Mar 27, 9:39 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
On Mar 26, 8:41 pm, Pratap <pratap.i...@gmail.com> wrote:



On Mar 27, 6:39 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:

On Mar 26, 7:53 am, Pratap <pratap.i...@gmail.com> wrote:

The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be used
by the MGTs.  In the Virtex-II Pro FPGA family the MGT reference clock
pins were normal I/Os that had extra dedicated routing to the MGTs.

Are you using a Xilinx board?  If so which one is it?

What are the IO location constraints that you are using for the output
and input paths?

Ed McGettigan
--
Xilinx Inc.

Hello,
I am using the Virtex II Pro development board for my project.
I am pasting all the IO constraints written to the ucf file.
The signals to take out and then feed in are "inp_for_TI_chip" and
"op_from_TI_chip" respectively.

NET "reset_in" LOC = "AH1" | IOSTANDARD = LVCMOS25;
#LEFT P/B

NET "clk_in" LOC = "G15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_P

NET "samp_clk" LOC = "F15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_N

NET "op_from_TI_chip"  LOC = "A6" | IOSTANDARD = LVCMOS25;
#MGT_TXP

NET "inp_for_TI_chip"  LOC = "A7" | IOSTANDARD = LVCMOS25 | SLEW > > > > FAST | DRIVE = 8 ;
#MGT_TXN

NET "ti_delay_chip_cntl"  LOC = "R9" | IOSTANDARD = LVCMOS25 | SLEW > > > > FAST | DRIVE = 8 ;
#J5-11

NET "dir_fine_delay"  LOC = "P1" | IOSTANDARD = LVCMOS25 | SLEW = FAST
| DRIVE = 8 ;
#J5-15

NET "board_in1"  LOC = "AB1" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-27

NET "board_in2"  LOC = "W8" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-35

NET "cleaned_clk1"  LOC = "R3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-31

NET "cleaned_clk2"  LOC = "U3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-39

NET "status(3)" LOC = "AC4" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(2)" LOC = "AC3" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(1)" LOC = "AA6" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(0)" LOC = "AA5" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;

Thanks,
Pratap

The UCF file constraints have regular IO location assignments to A7
and A6 which are the MGT TXP/TXN pins.  These locations are not valid
for anything other than MGT TXP/TXN pins and your original post
indicated that you had changed these to other locations and it worked..

I'm confused.  What exactly is your question or problem?

Ed McGettigan
--
Xilinx Inc.

Yes,
This is the ucf file that is not working. The ucf file that ensures
that there is toggling at all the signal ports is as follows.

NET "op_from_TI_chip"  LOC = "F16" | IOSTANDARD = LVCMOS25;
#MGT_CLK_P

NET "inp_for_TI_chip"  LOC = "G16" | IOSTANDARD = LVCMOS25 | SLEW > > FAST | DRIVE = 8 ;
#MGT_CLK_N

My exact problem is in understanding why in the case when I connect
the pins intended to be interfaced with the other chip to F16 and
G16(The externally non-accessible ports on board) , I get the signals
at the output port. If I connect those two signals to any other  pin,
it doesn't seem to work.
I hope the problem is clear now.

Thanks,
Pratap- Hide quoted text -

- Show quoted text -

Sorry, it still isn't very clear and you still haven't identified
which exact board you are using (vendor and model).

As I said twice already, the MGT TXP/TXN pins A6/A7 cannot be used for
anything other that the MGT.  For this device pins F16 and G16 are
regular IO and also MGT reference clock input pins so they can be used
for inputs or outputs.

If I connect those two signals to any other  pin,
it doesn't seem to work.

It isn't clear what you mean by any other pin and what doesn't work.

Ed McGettigan
--
Xilinx Inc.
Click to expand...
OK.
Let me rephrase the problem.
All I want is, I want to take a signal out of the Xilinx Virtex II Pro
board which is fed to the FPGA pin "G15" (EXT_CLK_N).
If I give a signal to "G15" (EXT_CLK_N) and take it out of FPGA
through the pin "F15" (EXT_CLK_P), it works absolutely fine.
But when I use both the pins F15 and G15 for two different input
signals, and want to take a delayed version of the signal fed to
"G15", by routing it through any of the pins in the connector series
located on J5 or J6 or J37(Eg AC6 on J37-A14), it doesn't come out. I
want to stimulate another chip with this delayed signal coming from
FPGA. The P&R completes without any problem when I use the Pin J37-A14
or any other pin, but when I am checking the signal at that pin by
connecting an oscilloscope probe there, I don't see any signal there.
This is what I mean by, things don't work. Is is there any issue in
taking out the signals connected to F15 or G15 once I use both of
those pins as inputs? If yes, why so and what is the way around?
I hope the question is more straight forward now and thanks for the
patience shown in understanding the issue.
Thanks,
Pratap
 
On Mar 27, 9:39 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
On Mar 26, 8:41 pm, Pratap <pratap.i...@gmail.com> wrote:



On Mar 27, 6:39 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:

On Mar 26, 7:53 am, Pratap <pratap.i...@gmail.com> wrote:

The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be used
by the MGTs.  In the Virtex-II Pro FPGA family the MGT reference clock
pins were normal I/Os that had extra dedicated routing to the MGTs.

Are you using a Xilinx board?  If so which one is it?

What are the IO location constraints that you are using for the output
and input paths?

Ed McGettigan
--
Xilinx Inc.

Hello,
I am using the Virtex II Pro development board for my project.
I am pasting all the IO constraints written to the ucf file.
The signals to take out and then feed in are "inp_for_TI_chip" and
"op_from_TI_chip" respectively.

NET "reset_in" LOC = "AH1" | IOSTANDARD = LVCMOS25;
#LEFT P/B

NET "clk_in" LOC = "G15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_P

NET "samp_clk" LOC = "F15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_N

NET "op_from_TI_chip"  LOC = "A6" | IOSTANDARD = LVCMOS25;
#MGT_TXP

NET "inp_for_TI_chip"  LOC = "A7" | IOSTANDARD = LVCMOS25 | SLEW > > > > FAST | DRIVE = 8 ;
#MGT_TXN

NET "ti_delay_chip_cntl"  LOC = "R9" | IOSTANDARD = LVCMOS25 | SLEW > > > > FAST | DRIVE = 8 ;
#J5-11

NET "dir_fine_delay"  LOC = "P1" | IOSTANDARD = LVCMOS25 | SLEW = FAST
| DRIVE = 8 ;
#J5-15

NET "board_in1"  LOC = "AB1" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-27

NET "board_in2"  LOC = "W8" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-35

NET "cleaned_clk1"  LOC = "R3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-31

NET "cleaned_clk2"  LOC = "U3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-39

NET "status(3)" LOC = "AC4" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(2)" LOC = "AC3" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(1)" LOC = "AA6" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(0)" LOC = "AA5" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;

Thanks,
Pratap

The UCF file constraints have regular IO location assignments to A7
and A6 which are the MGT TXP/TXN pins.  These locations are not valid
for anything other than MGT TXP/TXN pins and your original post
indicated that you had changed these to other locations and it worked..

I'm confused.  What exactly is your question or problem?

Ed McGettigan
--
Xilinx Inc.

Yes,
This is the ucf file that is not working. The ucf file that ensures
that there is toggling at all the signal ports is as follows.

NET "op_from_TI_chip"  LOC = "F16" | IOSTANDARD = LVCMOS25;
#MGT_CLK_P

NET "inp_for_TI_chip"  LOC = "G16" | IOSTANDARD = LVCMOS25 | SLEW > > FAST | DRIVE = 8 ;
#MGT_CLK_N

My exact problem is in understanding why in the case when I connect
the pins intended to be interfaced with the other chip to F16 and
G16(The externally non-accessible ports on board) , I get the signals
at the output port. If I connect those two signals to any other  pin,
it doesn't seem to work.
I hope the problem is clear now.

Thanks,
Pratap- Hide quoted text -

- Show quoted text -

Sorry, it still isn't very clear and you still haven't identified
which exact board you are using (vendor and model).

As I said twice already, the MGT TXP/TXN pins A6/A7 cannot be used for
anything other that the MGT.  For this device pins F16 and G16 are
regular IO and also MGT reference clock input pins so they can be used
for inputs or outputs.

If I connect those two signals to any other  pin,
it doesn't seem to work.

It isn't clear what you mean by any other pin and what doesn't work.

Ed McGettigan
--
Xilinx Inc.
Click to expand...
OK.
Let me rephrase the problem.
All I want is, I want to take a signal out of the Xilinx Virtex II Pro
board which is fed to the FPGA pin "G15" (EXT_CLK_N).
If I give a signal to "G15" (EXT_CLK_N) and take it out of FPGA
through the pin "F15" (EXT_CLK_P), it works absolutely fine.
But when I use both the pins F15 and G15 for two different input
signals, and want to take a delayed version of the signal fed to
"G15", by routing it through any of the pins in the connector series
located on J5 or J6 or J37(Eg AC6 on J37-A14), it doesn't come out. I
want to stimulate another chip with this delayed signal coming from
FPGA. The P&R completes without any problem when I use the Pin J37-A14
or any other pin, but when I am checking the signal at that pin by
connecting an oscilloscope probe there, I don't see any signal there.
This is what I mean by, things don't work. Is is there any issue in
taking out the signals connected to F15 or G15 once I use both of
those pins as inputs? If yes, why so and what is the way around?
I hope the question is more straight forward now and thanks for the
patience shown in understanding the issue.
Thanks,
Pratap
 
On Mar 27, 9:57 am, Pratap <pratap.i...@gmail.com> wrote:
On Mar 27, 9:39 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:





On Mar 26, 8:41 pm, Pratap <pratap.i...@gmail.com> wrote:

On Mar 27, 6:39 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:

On Mar 26, 7:53 am, Pratap <pratap.i...@gmail.com> wrote:

The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be used
by the MGTs.  In the Virtex-II Pro FPGA family the MGT reference clock
pins were normal I/Os that had extra dedicated routing to the MGTs.

Are you using a Xilinx board?  If so which one is it?

What are the IO location constraints that you are using for the output
and input paths?

Ed McGettigan
--
Xilinx Inc.

Hello,
I am using the Virtex II Pro development board for my project.
I am pasting all the IO constraints written to the ucf file.
The signals to take out and then feed in are "inp_for_TI_chip" and
"op_from_TI_chip" respectively.

NET "reset_in" LOC = "AH1" | IOSTANDARD = LVCMOS25;
#LEFT P/B

NET "clk_in" LOC = "G15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_P

NET "samp_clk" LOC = "F15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_N

NET "op_from_TI_chip"  LOC = "A6" | IOSTANDARD = LVCMOS25;
#MGT_TXP

NET "inp_for_TI_chip"  LOC = "A7" | IOSTANDARD = LVCMOS25 | SLEW > > > > > FAST | DRIVE = 8 ;
#MGT_TXN

NET "ti_delay_chip_cntl"  LOC = "R9" | IOSTANDARD = LVCMOS25 | SLEW > > > > > FAST | DRIVE = 8 ;
#J5-11

NET "dir_fine_delay"  LOC = "P1" | IOSTANDARD = LVCMOS25 | SLEW = FAST
| DRIVE = 8 ;
#J5-15

NET "board_in1"  LOC = "AB1" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-27

NET "board_in2"  LOC = "W8" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-35

NET "cleaned_clk1"  LOC = "R3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-31

NET "cleaned_clk2"  LOC = "U3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-39

NET "status(3)" LOC = "AC4" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(2)" LOC = "AC3" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(1)" LOC = "AA6" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(0)" LOC = "AA5" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;

Thanks,
Pratap

The UCF file constraints have regular IO location assignments to A7
and A6 which are the MGT TXP/TXN pins.  These locations are not valid
for anything other than MGT TXP/TXN pins and your original post
indicated that you had changed these to other locations and it worked.

I'm confused.  What exactly is your question or problem?

Ed McGettigan
--
Xilinx Inc.

Yes,
This is the ucf file that is not working. The ucf file that ensures
that there is toggling at all the signal ports is as follows.

NET "op_from_TI_chip"  LOC = "F16" | IOSTANDARD = LVCMOS25;
#MGT_CLK_P

NET "inp_for_TI_chip"  LOC = "G16" | IOSTANDARD = LVCMOS25 | SLEW > > > FAST | DRIVE = 8 ;
#MGT_CLK_N

My exact problem is in understanding why in the case when I connect
the pins intended to be interfaced with the other chip to F16 and
G16(The externally non-accessible ports on board) , I get the signals
at the output port. If I connect those two signals to any other  pin,
it doesn't seem to work.
I hope the problem is clear now.

Thanks,
Pratap- Hide quoted text -

- Show quoted text -

Sorry, it still isn't very clear and you still haven't identified
which exact board you are using (vendor and model).

As I said twice already, the MGT TXP/TXN pins A6/A7 cannot be used for
anything other that the MGT.  For this device pins F16 and G16 are
regular IO and also MGT reference clock input pins so they can be used
for inputs or outputs.

If I connect those two signals to any other  pin,
it doesn't seem to work.

It isn't clear what you mean by any other pin and what doesn't work.

Ed McGettigan
--
Xilinx Inc.

OK.
Let me rephrase the problem.
All I want is, I want to take a signal out of the Xilinx Virtex II Pro
board which is fed to the FPGA pin "G15" (EXT_CLK_N).
If I give a signal to "G15" (EXT_CLK_N) and take it out of FPGA
through the pin "F15" (EXT_CLK_P), it works absolutely fine.
But when I use both the pins F15 and G15 for two different input
signals, and want to take a delayed version of the signal fed to
"G15", by routing it through any of the pins in the connector series
located on J5 or J6 or J37(Eg AC6 on J37-A14), it doesn't come out. I
want to stimulate another chip with this delayed signal coming from
FPGA. The P&R completes without any problem when I use the Pin J37-A14
or any other pin, but when I am checking the signal at that pin by
connecting an oscilloscope probe there, I don't see any signal there.
This is what I mean by, things don't work. Is is there any issue in
taking out the signals connected to F15 or G15 once I use both of
those pins as inputs? If yes, why so and what is the way around?
I hope the question is more straight forward now and thanks for the
patience shown in understanding the issue.
Thanks,
Pratap- Hide quoted text -

- Show quoted text -
Click to expand...
Pratap,

You still haven't said what board you are using. who made the board
and what is the model name? This is very important information.

Ed McGettigan
--
Xilinx Inc.
 
On Mar 28, 2:25 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
On Mar 27, 9:57 am, Pratap <pratap.i...@gmail.com> wrote:



On Mar 27, 9:39 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:

On Mar 26, 8:41 pm, Pratap <pratap.i...@gmail.com> wrote:

On Mar 27, 6:39 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:

On Mar 26, 7:53 am, Pratap <pratap.i...@gmail.com> wrote:

The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be used
by the MGTs.  In the Virtex-II Pro FPGA family the MGT reference clock
pins were normal I/Os that had extra dedicated routing to the MGTs.

Are you using a Xilinx board?  If so which one is it?

What are the IO location constraints that you are using for the output
and input paths?

Ed McGettigan
--
Xilinx Inc.

Hello,
I am using the Virtex II Pro development board for my project.
I am pasting all the IO constraints written to the ucf file.
The signals to take out and then feed in are "inp_for_TI_chip" and
"op_from_TI_chip" respectively.

NET "reset_in" LOC = "AH1" | IOSTANDARD = LVCMOS25;
#LEFT P/B

NET "clk_in" LOC = "G15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_P

NET "samp_clk" LOC = "F15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_N

NET "op_from_TI_chip"  LOC = "A6" | IOSTANDARD = LVCMOS25;
#MGT_TXP

NET "inp_for_TI_chip"  LOC = "A7" | IOSTANDARD = LVCMOS25 | SLEW > > > > > > FAST | DRIVE = 8 ;
#MGT_TXN

NET "ti_delay_chip_cntl"  LOC = "R9" | IOSTANDARD = LVCMOS25 | SLEW > > > > > > FAST | DRIVE = 8 ;
#J5-11

NET "dir_fine_delay"  LOC = "P1" | IOSTANDARD = LVCMOS25 | SLEW = FAST
| DRIVE = 8 ;
#J5-15

NET "board_in1"  LOC = "AB1" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-27

NET "board_in2"  LOC = "W8" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-35

NET "cleaned_clk1"  LOC = "R3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-31

NET "cleaned_clk2"  LOC = "U3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-39

NET "status(3)" LOC = "AC4" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(2)" LOC = "AC3" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(1)" LOC = "AA6" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(0)" LOC = "AA5" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;

Thanks,
Pratap

The UCF file constraints have regular IO location assignments to A7
and A6 which are the MGT TXP/TXN pins.  These locations are not valid
for anything other than MGT TXP/TXN pins and your original post
indicated that you had changed these to other locations and it worked.

I'm confused.  What exactly is your question or problem?

Ed McGettigan
--
Xilinx Inc.

Yes,
This is the ucf file that is not working. The ucf file that ensures
that there is toggling at all the signal ports is as follows.

NET "op_from_TI_chip"  LOC = "F16" | IOSTANDARD = LVCMOS25;
#MGT_CLK_P

NET "inp_for_TI_chip"  LOC = "G16" | IOSTANDARD = LVCMOS25 | SLEW > > > > FAST | DRIVE = 8 ;
#MGT_CLK_N

My exact problem is in understanding why in the case when I connect
the pins intended to be interfaced with the other chip to F16 and
G16(The externally non-accessible ports on board) , I get the signals
at the output port. If I connect those two signals to any other  pin,
it doesn't seem to work.
I hope the problem is clear now.

Thanks,
Pratap- Hide quoted text -

- Show quoted text -

Sorry, it still isn't very clear and you still haven't identified
which exact board you are using (vendor and model).

As I said twice already, the MGT TXP/TXN pins A6/A7 cannot be used for
anything other that the MGT.  For this device pins F16 and G16 are
regular IO and also MGT reference clock input pins so they can be used
for inputs or outputs.

If I connect those two signals to any other  pin,
it doesn't seem to work.

It isn't clear what you mean by any other pin and what doesn't work.

Ed McGettigan
--
Xilinx Inc.

OK.
Let me rephrase the problem.
All I want is, I want to take a signal out of the Xilinx Virtex II Pro
board which is fed to the FPGA pin "G15" (EXT_CLK_N).
If I give a signal to "G15" (EXT_CLK_N) and take it out of FPGA
through the pin "F15" (EXT_CLK_P), it works absolutely fine.
But when I use both the pins F15 and G15 for two different input
signals, and want to take a delayed version of the signal fed to
"G15", by routing it through any of the pins in the connector series
located on J5 or J6 or J37(Eg AC6 on J37-A14), it doesn't come out. I
want to stimulate another chip with this delayed signal coming from
FPGA. The P&R completes without any problem when I use the Pin J37-A14
or any other pin, but when I am checking the signal at that pin by
connecting an oscilloscope probe there, I don't see any signal there.
This is what I mean by, things don't work. Is is there any issue in
taking out the signals connected to F15 or G15 once I use both of
those pins as inputs? If yes, why so and what is the way around?
I hope the question is more straight forward now and thanks for the
patience shown in understanding the issue.
Thanks,
Pratap- Hide quoted text -

- Show quoted text -

Pratap,

You still haven't said what board you are using. who made the board
and what is the model name?  This is very important information.

Ed McGettigan
--
Xilinx Inc.
Click to expand...
Sorry,
Actually, it never struck to my mind that there are other varieties of
Xilinx Virtex-II Pro.
Here is the Target Device name: "Virtex-II Pro XC2VP30-7ff896"
Product link: http://www.xilinx.com/products/devkits/XUPV2P.htm
Image: http://www.xilinx.com/products/devkits/XUPV2P-image.htm
Thanks,
Pratap
 
On Mar 27, 3:23 pm, Pratap <pratap.i...@gmail.com> wrote:
On Mar 28, 2:25 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:





On Mar 27, 9:57 am, Pratap <pratap.i...@gmail.com> wrote:

On Mar 27, 9:39 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:

On Mar 26, 8:41 pm, Pratap <pratap.i...@gmail.com> wrote:

On Mar 27, 6:39 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:

On Mar 26, 7:53 am, Pratap <pratap.i...@gmail.com> wrote:

The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be used
by the MGTs.  In the Virtex-II Pro FPGA family the MGT reference clock
pins were normal I/Os that had extra dedicated routing to the MGTs.

Are you using a Xilinx board?  If so which one is it?

What are the IO location constraints that you are using for the output
and input paths?

Ed McGettigan
--
Xilinx Inc.

Hello,
I am using the Virtex II Pro development board for my project..
I am pasting all the IO constraints written to the ucf file.
The signals to take out and then feed in are "inp_for_TI_chip" and
"op_from_TI_chip" respectively.

NET "reset_in" LOC = "AH1" | IOSTANDARD = LVCMOS25;
#LEFT P/B

NET "clk_in" LOC = "G15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_P

NET "samp_clk" LOC = "F15" | IOSTANDARD = LVCMOS25;
#EXTERNAL_CLOCK_N

NET "op_from_TI_chip"  LOC = "A6" | IOSTANDARD = LVCMOS25;
#MGT_TXP

NET "inp_for_TI_chip"  LOC = "A7" | IOSTANDARD = LVCMOS25 | SLEW > > > > > > > FAST | DRIVE = 8 ;
#MGT_TXN

NET "ti_delay_chip_cntl"  LOC = "R9" | IOSTANDARD = LVCMOS25 | SLEW > > > > > > > FAST | DRIVE = 8 ;
#J5-11

NET "dir_fine_delay"  LOC = "P1" | IOSTANDARD = LVCMOS25 | SLEW = FAST
| DRIVE = 8 ;
#J5-15

NET "board_in1"  LOC = "AB1" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-27

NET "board_in2"  LOC = "W8" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J6-35

NET "cleaned_clk1"  LOC = "R3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-31

NET "cleaned_clk2"  LOC = "U3" | IOSTANDARD = LVCMOS25 | SLEW = FAST |
DRIVE = 8 ;
#J5-39

NET "status(3)" LOC = "AC4" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(2)" LOC = "AC3" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(1)" LOC = "AA6" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;
NET "status(0)" LOC = "AA5" | IOSTANDARD = LVCMOS25 | SLEW = SLOW |
DRIVE = 12 ;

Thanks,
Pratap

The UCF file constraints have regular IO location assignments to A7
and A6 which are the MGT TXP/TXN pins.  These locations are not valid
for anything other than MGT TXP/TXN pins and your original post
indicated that you had changed these to other locations and it worked.

I'm confused.  What exactly is your question or problem?

Ed McGettigan
--
Xilinx Inc.

Yes,
This is the ucf file that is not working. The ucf file that ensures
that there is toggling at all the signal ports is as follows.

NET "op_from_TI_chip"  LOC = "F16" | IOSTANDARD = LVCMOS25;
#MGT_CLK_P

NET "inp_for_TI_chip"  LOC = "G16" | IOSTANDARD = LVCMOS25 | SLEW > > > > > FAST | DRIVE = 8 ;
#MGT_CLK_N

My exact problem is in understanding why in the case when I connect
the pins intended to be interfaced with the other chip to F16 and
G16(The externally non-accessible ports on board) , I get the signals
at the output port. If I connect those two signals to any other  pin,
it doesn't seem to work.
I hope the problem is clear now.

Thanks,
Pratap- Hide quoted text -

- Show quoted text -

Sorry, it still isn't very clear and you still haven't identified
which exact board you are using (vendor and model).

As I said twice already, the MGT TXP/TXN pins A6/A7 cannot be used for
anything other that the MGT.  For this device pins F16 and G16 are
regular IO and also MGT reference clock input pins so they can be used
for inputs or outputs.

If I connect those two signals to any other  pin,
it doesn't seem to work.

It isn't clear what you mean by any other pin and what doesn't work..

Ed McGettigan
--
Xilinx Inc.

OK.
Let me rephrase the problem.
All I want is, I want to take a signal out of the Xilinx Virtex II Pro
board which is fed to the FPGA pin "G15" (EXT_CLK_N).
If I give a signal to "G15" (EXT_CLK_N) and take it out of FPGA
through the pin "F15" (EXT_CLK_P), it works absolutely fine.
But when I use both the pins F15 and G15 for two different input
signals, and want to take a delayed version of the signal fed to
"G15", by routing it through any of the pins in the connector series
located on J5 or J6 or J37(Eg AC6 on J37-A14), it doesn't come out. I
want to stimulate another chip with this delayed signal coming from
FPGA. The P&R completes without any problem when I use the Pin J37-A14
or any other pin, but when I am checking the signal at that pin by
connecting an oscilloscope probe there, I don't see any signal there.
This is what I mean by, things don't work. Is is there any issue in
taking out the signals connected to F15 or G15 once I use both of
those pins as inputs? If yes, why so and what is the way around?
I hope the question is more straight forward now and thanks for the
patience shown in understanding the issue.
Thanks,
Pratap- Hide quoted text -

- Show quoted text -

Pratap,

You still haven't said what board you are using. who made the board
and what is the model name?  This is very important information.

Ed McGettigan
--
Xilinx Inc.

Sorry,
Actually, it never struck to my mind that there are other varieties of
Xilinx Virtex-II Pro.
Here is the Target Device name: "Virtex-II Pro XC2VP30-7ff896"
Product link:http://www.xilinx.com/products/devkits/XUPV2P.htm
Image:http://www.xilinx.com/products/devkits/XUPV2P-image.htm
Thanks,
Pratap- Hide quoted text -

- Show quoted text -
Click to expand...
Virtex-II Pro is a FPGA family which is collection different device
sizes and package options with a common architecture. Boards that use
FPGAs are each unique implementations with a fixed set of features
that the FPGA design most conform to or it won't work.

The Xilinx XUP2VP board and your IO constraints have a couple of
problems:

1) G15/F15 are connected on the board with a 100 ohm termination
resistor

When you said that you "gave" a signal to G15 and "took" it from F15
the 100 ohm resistor provided a pass through of the signal and the
FPGA did not need to be involved. It isn't clear what is actually
happening on your setup. If the input did resolve to a 0/1 in the
FPGA then the output should drive the same value a few nanosconds
later. This would lead to some contention during this period and the
output waveform would not be clean. Your oscilloscope may be
filtering this out due to the short duration.

2) The VCCO for the banks that you are using are 3.3V

Bank 1 (F16/G16) and bank 3 (AC6) both have VCCO levels of 3.3V, but
your UCF file has defined these IOs as LVCMOS25. The output should
still be working, but without the correct drive strengths and levels.
The input functionality will depend on the voltage that is present on
the pin. It may resolve or it may not. You haven't said anything
about the actual device that you are trying to interface with so I
don't know what levels it is expecting and putting out. If the
levels are correct then nothing will work.

There is the possibilities that you have are not probing the correct
pin on the connector. I would suggest that you try outputting the
system clock to the desired pin to verify that you are probing/
connecting the right pin.

Ed McGettigan
--
Xilinx Inc.
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top