how to suspend a module in the middle of its operation (or h

[thomasc]

how to suspend a module in the middle of its operation (or how to implement
C 'goto' statement in Verilog)

Suppose we want to implement a hardware usng Verilog.
This hardware is composed of 3 modules(a, b, c). Module a begins first.
Depending on the result from module a, the next module to be executed can
be either module b or module c. In other words, if module a finishes its
operation without any problem, module b turns on and does its calculation.
But if a certain condition occurs during module a operation, module c
should be executed and module a should stop its operation(or be turned
off). I'm looking for a way to make module a stop its operation in such a
case.

This should be very similar to 'goto' statment in C language. I used
'disable' and named-block in Verilog to implement this and succeeded
simulation. However, while trying to synthesize it, Xilinx ISE6.3i gave an
error message("Unsupported Disable Statement") and failed sythesizing it.

Anyone plese let me know:
-how to make a module turn off itself in the midle of its operation or
-how to implement 'goto' statement in C language using Verilog.

Thanks much in advance!

 

[Berty]

Disable is indeed powerful command however it should as you notice be
used only for the "test bench" parts and not for the actual code.

Depend what you actually want to do there can be several way to solve
it including more "exotic" solution involve gated clock if the
reason require power saving, but assume the requirement is simple to
choose which module output to use than you can look on it as all 3
module a,b and c run in parallel and using a mux you decide which
output to use.

For example let say module a get x and y and generate za= x + y.

Than if za > 10 you want to use module b which will generate zb which
is zb = x

And if zb < 5 you want to use module c which will generate zc which is
zc = y - 3

Otherwise you want to just pass za.

So what you will end up is with each module calculate it own z value
and than use function of za as a selector for a mux which will decide
which output to pass.

Of course the above example is simple enough to put all in one module
not to mention if zb was something like x + 3 than using separate
module would result in more logic as you will be using two adder versus
using one adder and mux of the variable but this is a different aspect.

Have fun.