HOW TO: Stuffing Parameters in verilog tasks

[Raymond Bingham]

Anyone out there know how to pass verilog parameters to a verilog
task? Synopsys and Cadence both compile okay with parameters in the
task function, but I don't know how to change them. Can you?

You can't put it in the parameter list.
You can't put a #(param) between the task call and the parameter list.

You can't put #(param) in front of a task, cuz that would be a
#(delay)
wouldn't it?

I tried using defparam, and it didn't like that, either...

Any ideas?

Best regards,

--Ray Bingham

 

[Andy Peters]

rbingham@dotcast.com (Raymond Bingham) wrote in message news:<c26550fd.0407121530.11bedcf0@posting.google.com>...

Anyone out there know how to pass verilog parameters to a verilog
task? Synopsys and Cadence both compile okay with parameters in the
task function, but I don't know how to change them. Can you?

You can't put it in the parameter list.
You can't put a #(param) between the task call and the parameter list.

You can't put #(param) in front of a task, cuz that would be a
#(delay)
wouldn't it?

I tried using defparam, and it didn't like that, either...

Pass the parameter as a task argument. For example,

module TaskTestModule;

parameter FOO = 2;
parameter BAR = 3;
parameter BLETCH = 666;

integer someint;

...

task DoSomething
(input integer this,
input integer that,
input integer theother,
output integer yecch);

begin : task_DoSomething
...
end // task_DoSomething
endtask // DoSomething

initial begin : TaskTest
DoSomething(FOO, BAR, BLETCH, someint);
end // TaskTest

endmodule // TaskTestModule

hope this helps,
-a

 

[Jonathan Bromley]

On 12 Jul 2004 16:30:20 -0700, rbingham@dotcast.com (Raymond Bingham)
wrote:

Anyone out there know how to pass verilog parameters to a verilog
task? Synopsys and Cadence both compile okay with parameters in the
task function, but I don't know how to change them. Can you?

If you want a value that's different every time the task is
called, simply pass it in the argument list. The "parameter"
is then an input argument of the task, and therefore a local
register of the task, so you have to be careful to avoid
writing to it inadvertently.

If you want a value that's different for some instances of the
task, but fixed for each and every call of a given instance of
the task, then you need to put the task in a module and
parameterise each instance of the module.

Parameters inside a task are fine, and you can "defparam" them
from outside the task by using the task name as part of
a hierarchical name (but that's not synthesisable, of course).
Such parameters, like any others, get a fixed value when the
simulation is elaborated, and can't be changed during simulation.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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[Raymond Bingham]

Jonathan Bromley <jonathan.bromley@doulos.com> wrote in message

Parameters inside a task are fine, and you can "defparam" them
from outside the task by using the task name as part of
a hierarchical name (but that's not synthesisable, of course).
Such parameters, like any others, get a fixed value when the
simulation is elaborated, and can't be changed during simulation.

Thanks for the comments, Jonathan. Don't care about synthesis,
cuz it's testbench work. The thing I like about parameters is you can
specify them in your code upon calling them, with defaults, so you
can pass in strings in a more manageable fashion... I realized
later that defparam would work, but not how I wanted it, so I've
given up on that approach.

Fixed length strings really stink in verilog. Admittedly it's not a
big deal in terms of a hardware language, but in terms of verification,
it makes the code a bit cumbersome.

Anyhow not a big deal... I've already worked out what I wanted to do.

--Ray