How to stop dummy transistors to be extracted?

[meghna]

Hi,
The dummy transistors are creating problem while doing LVS (in virtuoso).
If I don't want them to be extracted, what should I do? How to add the
'lvsIgnore' Property?

Thanks!

 

[S. Badel]

what tool?

meghna wrote:

Hi,
The dummy transistors are creating problem while doing LVS (in virtuoso).
If I don't want them to be extracted, what should I do? How to add the
'lvsIgnore' Property?

Thanks!

 

[meghna]

I am using Virtuoso tool of Cadence.

 

[Andrew Beckett]

On Fri, 11 Mar 2005 11:18:25 -0500, "meghna" <meghna@protected_id> wrote:

I am using Virtuoso tool of Cadence.

Virtuoso would be the layout editor - what is the extraction tool? If it is
a Cadence tool, it could be Dracula, Diva, Assura. Or it could be an
extraction tool from another company?

Virtuoso is not the extraction tool.

My guess is that it is probably Diva, but that's just a guess.

Andrew.

 

[meghna]

You are right. I am using Diva Design Rule Checker, Diva Parasitic
Extracter, and Diva Layout Vs. Schematic Verifier.

Regards

 

[Diva Physical Verificatio]

On Fri, 11 Mar 2005 23:24:56 -0500, "meghna" <meghna@protected_id>
wrote:

You are right. I am using Diva Design Rule Checker, Diva Parasitic
Extracter, and Diva Layout Vs. Schematic Verifier.

Regards

How do you define a transistor as being a dummy? There are a number of
techniques you can use depending on your definition.

The first is to define a dummy flag layer. On this layer you put shapes
over the dummy transistors and geomAndNot the shapes from the device
recognition layer before extractDevice. This works for any definition. I
consider this a dangerous practice since the dummy transistor may be
connected to the rest of the circuit in a way that affects behavior.

The second is to use pruneDevice in your LVS rules. This is preferred
since it only ignores the devices which are not part of the circuit. You
have to observe the connection conditions in the manual, but that is not
generally a problem. If the dummy is accidentally connected, this will
flag it.

The third is to define the dummy devices in the schematic as spares.
Connect them the same as you do in the layout. If all your dummy devices
are connected in parallel, as in the S/D/G/B to a power rail, then you
can get away with a single spare in the schematic. Use a flag value as
the width and length, like 0.0, and have your compare procedure accept
any values on the layout side when the schematic width and length are
the flag value. Or you can use real values and have the dummy sizes be
checked for correctness, but you would have to account for the number of
spares in the layout.