W
Weng Tianxiang
Guest
Hi,
I need your help.
I have 4 vhdl source files:
A-Package.vhd;
A1.vhd;
A2.vhd;
A3.vhd;
A-Package.vhd is a package defining all common functions and constants
used for all other modules.
If the 4 files are in the above order, Modelsim runs them without any
errors.
But with Xilinx 8.1i, some parameters saved in A-Package.vhd file are
not referenced correctly in other modules.
Should I compile A-Package.vhd first as an independent project and then
what to do?
Thank you.
Weng
I need your help.
I have 4 vhdl source files:
A-Package.vhd;
A1.vhd;
A2.vhd;
A3.vhd;
A-Package.vhd is a package defining all common functions and constants
used for all other modules.
If the 4 files are in the above order, Modelsim runs them without any
errors.
But with Xilinx 8.1i, some parameters saved in A-Package.vhd file are
not referenced correctly in other modules.
Should I compile A-Package.vhd first as an independent project and then
what to do?
Thank you.
Weng