How to solve layout Minimum Density Area across chip / CHIP

B

boki

Guest
Dear All:

When I using TSMC 0.35 2P4M process to layout, the DRC error report
these messages:

1. POLY Minimum Density Area across chip / CHIP Area must be >= XX%
2. M1 Minimum Density Area across chip / CHIP Area must be >= XX%
3. M2 Minimum Density Area across chip / CHIP Area must be >= XX%
4. M3 Minimum Density Area across chip / CHIP Area must be >= XX%
5. M4 Minimum Density Area across chip / CHIP Area must be >= XX%

But, in my layout design, I did't need these layers or area, could you
please give me some suggest?

Thanks!

Boki.
 
If you do not need POLY, then you have no transistors. If you do not
need even M1, then you have no interconnect. The area they are talking
about is the area of the chip, also known as your design.

Assuming you are using Diva, to find the area of the design which has
low density, try using a recent hot fix and a rule like the following.
Substitute whatever layer is the bounding rectangle of the design for
CHIP. Using geomBkgnd(0) might be enough. The resulting error markers
are the windows which have density that is too low.

drc(POLY CHIP coverage < 0.14 windowSize(10) stepSize(5)
keep "density < 0.14")

On 16 Sep 2003 22:53:44 -0700, bokiteam@ms21.hinet.net (boki) wrote:

Dear All:

When I using TSMC 0.35 2P4M process to layout, the DRC error report
these messages:

1. POLY Minimum Density Area across chip / CHIP Area must be >= XX%
2. M1 Minimum Density Area across chip / CHIP Area must be >= XX%
3. M2 Minimum Density Area across chip / CHIP Area must be >= XX%
4. M3 Minimum Density Area across chip / CHIP Area must be >= XX%
5. M4 Minimum Density Area across chip / CHIP Area must be >= XX%

But, in my layout design, I did't need these layers or area, could you
please give me some suggest?

Thanks!

Boki.
Click to expand...
 
usually you add dummy structures
check the design rules maybe they explain how to build these

"boki" <bokiteam@ms21.hinet.net> wrote in message
news:4c3c095a.0309162153.3a817543@posting.google.com...
Dear All:

When I using TSMC 0.35 2P4M process to layout, the DRC error report
these messages:

1. POLY Minimum Density Area across chip / CHIP Area must be >= XX%
2. M1 Minimum Density Area across chip / CHIP Area must be >= XX%
3. M2 Minimum Density Area across chip / CHIP Area must be >= XX%
4. M3 Minimum Density Area across chip / CHIP Area must be >= XX%
5. M4 Minimum Density Area across chip / CHIP Area must be >= XX%

But, in my layout design, I did't need these layers or area, could you
please give me some suggest?

Thanks!

Boki.
Click to expand...
 
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