how to simulate verilog with rom in modelsim?

[seanzhang]

I got error like this in modelsim:
# Loading work.top_tb
# Loading work.top
# Loading work.rom1
# ** Warning: (vsim-3010) [TSCALE] - Module 'rom1' has a `timescale
directive in effect, but previous modules do not.
# Region: /top_tb/top1/rom1_inst
# ** Error: (vsim-3033) D:/my project/FPGA logic/tb1/rom1.v(77):
Instantiation of 'altsyncram' failed. The design unit was not found.
# Region: /top_tb/top1/rom1_inst
# Searched libraries:
# work
# Error loading design

 

[seanzhang]

who can provide me a simple example about simulate verilog with rom in
modelsim?
I need it most

 

[Petter Gustad]

"seanzhang" <sean@iron-sword.com> writes:

I got error like this in modelsim:
....
Instantiation of 'altsyncram' failed. The design unit was not found.

You need to include the Altera library. You will find this in

[Quartus install directory]/eda/sim_lib/altera_mf.v


Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
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[Jason Zheng]

seanzhang wrote:

who can provide me a simple example about simulate verilog with rom in
modelsim?
I need it most

module pseudo_rom(addr, data)
input [1:0] addr;
output [15:0] data;

reg [15:0] data;

always @ (addr)
case (addr)
2'b00: data <= 16'h0001;
2'b01: data <= 16'h0002;
2'b10: data <= 16'b0003;
2'b11: data <= 16'b0004;
default: data <= 16'b0001;
endcase
endmodule

 

[Jason Zheng]

Jason Zheng wrote:

seanzhang wrote:

who can provide me a simple example about simulate verilog with rom in
modelsim?
I need it most


module pseudo_rom(addr, data)
input [1:0] addr;
output [15:0] data;

reg [15:0] data;

always @ (addr)
case (addr)
2'b00: data <= 16'h0001;
2'b01: data <= 16'h0002;
2'b10: data <= 16'b0003;
2'b11: data <= 16'b0004;
default: data <= 16'b0001;
endcase
endmodule
btw, anyone knows the best way to synthesize rom with actel FPGA? I'm

using simplicity

 

[seanzhang]

I compile them,but it seems that mif file is not loaded?
how to do this?I am really really puzzled