How to simulate PLL phase noise efficiently

[Gang Bu]

Hi, all:

I am working on a 24 GHz PLL with loop bandwith of 0.5MHz. Does anyone have
any segguestion on how to simulate the overall closed-loop phase noise
(postlayout) efficiently? I guess this is a well known problem. It seems to
me that I need a huge hard disk, as well as several days of waiting.
Appreciate your help.

Best regards,
Gang

 

[Andrew Beckett]

On Tue, 9 Jan 2007 14:52:26 -0500, "Gang Bu" <gang.bu@gmail.com> wrote:

Hi, all:

I am working on a 24 GHz PLL with loop bandwith of 0.5MHz. Does anyone have
any segguestion on how to simulate the overall closed-loop phase noise
(postlayout) efficiently? I guess this is a well known problem. It seems to
me that I need a huge hard disk, as well as several days of waiting.
Appreciate your help.

Best regards,
Gang

A good place to look is:

http://www.designers-guide.org/Analysis/PLLnoise+jitter.pdf

Andrew.
--
Andrew Beckett
Principal European Technology Leader
Cadence Design Systems, UK.