How to simulate a Verilog model with some VHDL module iside

[subin]

Hi guys,
I have a model with top and some of the sub modules in verilog and
some blocks in vhdl.Is it possible to combine both language model and
simulate. I don't want to convert my vhdl modules to verilog.

thanks in advance.
Subin

 

[Mike Treseler]

subin wrote:

Hi guys,
I have a model with top and some of the sub modules in verilog and
some blocks in vhdl.Is it possible to combine both language model and
simulate.

It's possible, but not free.
Modelsim requires that I have one vhdl license
and one verilog license to cover this case.

What you can do for less money is look at the code
on an RTL viewer or make vhdl or verilog netlists
using xst or quartus.

I don't want to convert my vhdl modules to verilog.

I applaud you for that.
How about converting those verilog modules to vhdl

-- Mike Treseler