How to signextend or round

[blakaxe]

wire [OUT_WIDTH-1:0] output;
wire [15:0] temp;

I want to assign temp to output
assign output = temp;

but depending on OUT_WIDTH, I want to either sign extend(if OUTWIDTH

16 bits) or round(if OUT_WIDTH < 16 bits) temp to match the bitwidth

of output.

What is the best way to do this?
Thanks

 

[pallav]

On Aug 5, 3:40 pm, blakaxe <blak...@gmail.com> wrote:

 output;
wire  [15:0]         temp;

I want to assign temp to output
assign output = temp;

but depending on OUT_WIDTH, I want to either sign extend(if OUTWIDTH

16 bits) or round(if OUT_WIDTH < 16 bits) temp to match the bitwidth
of output.

What is the best way to do this?
Thanks

You don't have to worry about round. If output is less than 16 bits,
assign output = temp
will take the lower bits of temp and disregard the upper bits.

If output is more than 16 bits, the upper bits of the output will be
zero.

However, unless there is a good reason for doing this, it doesn't
sound like
a very good practice. Easy to introduce bugs and can be hard to spot
these
types of problems.

The way to sign extend if OUT_WIDTH is greater than 16 bits will be as
follows:

assign output = {{OUT_WIDTH-16{temp[15]}, temp};

Kind regards.

 

On Aug 5, 3:40 pm, blakaxe <blak...@gmail.com> wrote:

 output;
wire  [15:0]         temp;

I want to assign temp to output
assign output = temp;

but depending on OUT_WIDTH, I want to either sign extend(if OUTWIDTH

16 bits) or round(if OUT_WIDTH < 16 bits) temp to match the bitwidth
of output.

I am not sure what you mean by "round". An assignment to a narrower
width will automatically discard the extra upper bits and assign the
lower ones.

If you want sign-extension when OUTWIDTH > 16, all you have to do is
declare temp to be signed, i.e. "wire signed [15:0] temp". The
signedness of the left-hand side of the assignment doesn't matter. If
temp is not declared to be signed, it will be unsigned, and you will
get zero-extension instead.

This assumes your tools support this Verilog-2001 feature. Otherwise
you will have to use an explicit replication of the sign bit, as
pallav suggested. However, some tools might not accept the negative
replication count that would occur when OUTWIDTH < 16. For those that
do, it doesn't matter what result they produce, since those bits will
be discarded during the assignment anyway.