How to share Video-RAM between VGA Controller and CPU ?

[james]

On Thu, 10 Jan 2008 07:49:05 -0800 (PST), "psihodelia@googlemail.com"
<psihodelia@googlemail.com> wrote:

|I have only one SRAM IC and one FPGA.
|
|Low addresses of SRAM are used to keep video buffer that should be
|updated very rapidly, but the same IC has to keep also CPU
|instructions in the area of the upper addresses. Global clock of FPGA
|is 50 MHz. VGA Controller reads video buffer on 25 MHz. At the same
|time, CPU has to have enough time to fetch instructions, process
|program's memory, and update video memory - without big lag.
|
|VGA Controller reads hole video buffer 60 times per sec. It remains a
|bit time for CPU on back/front vertical porch+sync and very short time
|on back/front horizontal porch+sync.
|
|What could be the smartest solution in such situation?
|
|-------------

There is an old technique used years ago with slower CPUs and RAM that
was called IDMA(Interleaved Direct Memory Access??). You can
interleave the reads to the ram by the video section and the CPU by
using half the machine cycle. Example would be to have the CPU access
the ram during the second half of the clock cycle and the video during
the first half. You would have to multiplex the video and CPU
addresses and synch them with the CPU clock cycle, especially if it is
slower than the video read clock. This would keep you from having to
halt the CPU during video ram buffer reads.

This technique though does have its limits. Your access time for the
SRAM will need to be at least half that of the CPU clock period or
faster. 20nS SRAM access time will dictate a minimum CPU machine cycle
time of 40nS(25 MHz).

james

 

I have only one SRAM IC and one FPGA.

Low addresses of SRAM are used to keep video buffer that should be
updated very rapidly, but the same IC has to keep also CPU
instructions in the area of the upper addresses. Global clock of FPGA
is 50 MHz. VGA Controller reads video buffer on 25 MHz. At the same
time, CPU has to have enough time to fetch instructions, process
program's memory, and update video memory - without big lag.

VGA Controller reads hole video buffer 60 times per sec. It remains a
bit time for CPU on back/front vertical porch+sync and very short time
on back/front horizontal porch+sync.

What could be the smartest solution in such situation?

If the RAM cycle time is under 20ns and the video needs to read it
only once every 40ns, I'd suggest that you allocate alternate 20ns
periods to the video and CPU. This will give predictable CPU response
times (independent of the position in the video line or field cycle).

If you need to squeeze out maximum performance then you could allocate
all 20ns periods to the CPU during line or field blanking. I'd guess
that this would make only about 15% more RAM cycles available to the
CPU and the consequent increase in CPU throughput must be less than
that (especially if it has a cache inside the FPGA), so it won't
usually be worth the extra complexity.

How does this concern VHDL?

Mike

 

I have only one SRAM IC and one FPGA.

Low addresses of SRAM are used to keep video buffer that should be
updated very rapidly, but the same IC has to keep also CPU
instructions in the area of the upper addresses. Global clock of FPGA
is 50 MHz. VGA Controller reads video buffer on 25 MHz. At the same
time, CPU has to have enough time to fetch instructions, process
program's memory, and update video memory - without big lag.

VGA Controller reads hole video buffer 60 times per sec. It remains a
bit time for CPU on back/front vertical porch+sync and very short time
on back/front horizontal porch+sync.

What could be the smartest solution in such situation?

If the RAM cycle time is under 20ns and the video needs to read it
only once every 40ns, I'd suggest that you allocate alternate 20ns
periods to the video and CPU. This will give predictable CPU response
times (independent of the position in the video line or field cycle).

If you need to squeeze out maximum performance then you could allocate
all 20ns periods to the CPU during line or field blanking. I'd guess
that this would make only about 15% more RAM cycles available to the
CPU and the consequent increase in CPU throughput must be less than
that (especially if it has a cache inside the FPGA), so it won't
usually be worth the extra complexity.

How does this concern VHDL?

Mike

 

[psihodelia@googlemail.com]

I have only one SRAM IC and one FPGA.

Low addresses of SRAM are used to keep video buffer that should be
updated very rapidly, but the same IC has to keep also CPU
instructions in the area of the upper addresses. Global clock of FPGA
is 50 MHz. VGA Controller reads video buffer on 25 MHz. At the same
time, CPU has to have enough time to fetch instructions, process
program's memory, and update video memory - without big lag.

VGA Controller reads hole video buffer 60 times per sec. It remains a
bit time for CPU on back/front vertical porch+sync and very short time
on back/front horizontal porch+sync.

What could be the smartest solution in such situation?