How to run Modelsim for VHDL without using GUI..

P

priya

Guest
Hi all,

I am new to VHDl....But I am having knowleage in Verilog.
Here I have a doubt,How to run ModelSim for VHDL without using GUI.like
how to run modelsim for VHDL using Commandline operation.I am using
MOdelsim SE 6.1a version in Windows Xp.

For example like Verilog I worked Icarus Tool for simulating Verilog
code using Commandline mode..


like that way I need to run modelsim for VHDL?
and also I have to link the Fli with ModelSim VHDL..

Plz specify the commandline for Using FLI also.....

If anyone having answers,plz let me...


Thanks
Regards,
priya
 
How to run ModelSim for VHDL without using GUI.like
how to run modelsim for VHDL using Commandline operation.I am using
MOdelsim SE 6.1a version in Windows Xp.
You can use the command line to issue ModelSim commands (all of which
Click to expand...
are enumerated in Command Reference Manual of ModelSim). Additionally,
you can write a script (where you can combine ModelSim commands with
appropriate Tcl constructs) for running commands in batch mode. This
file (which is saved in .do format) can then be used to perform a
number of operations in series.

like that way I need to run modelsim for VHDL?
For VHDL, many of the commands are same except for compilation,
Click to expand...
simulation etc. For example "vlog" is used for Verilog compilation
while "vcom" for VHDL. All these are well explained in Command
Reference. If the command is same for both the languages, it may be
some construct/switch which can differ. Essentially, there is not much
difference in running the software for either of the languages from
command line, provided you have license for both the languages!
 
Hi,

thanks for ur response...I got the info from reference manual as u
said ...

Still i have one doubt ...when i type vsim in command line,the ModelSim
GUI editor opened automatically..So i Cound't type run command in
commandline.....I want to run vhdl code only in command line need not
to use Modelsim GUI editor to run the VHDL Code....
 
Hi all,

I want to display the VHDL input and output in commandline

like verilog we have function call $display,using $display we can
display the input and output..

is there any function to display the vhdl input and output in
commandline ?


regds,
priya
 
See:

http://www.noveldv.com/verif/hdl_faq/index.html

HTH
Ajeetha
www.noveldv.com

priya wrote:
Hi all,

I want to display the VHDL input and output in commandline

like verilog we have function call $display,using $display we can
display the input and output..

is there any function to display the vhdl input and output in
commandline ?


regds,
priya
Click to expand...
 
Hi all,

I have one more doubt..I want to send input to the VHDL code
using FLI Call.I have writen fli code ,it is in example.c file.I am
having two .vhd code called as test.vhd,foreigh.vhdl..

I am using gcc compiler to compile the FLI code.how to link fli and
vhdl code in the command line...


regds,
priya



Ajeetha wrote:
See:

http://www.noveldv.com/verif/hdl_faq/index.html

HTH
Ajeetha
www.noveldv.com

priya wrote:
Hi all,

I want to display the VHDL input and output in commandline

like verilog we have function call $display,using $display we can
display the input and output..

is there any function to display the vhdl input and output in
commandline ?


regds,
priya
Click to expand...
 
Priya,
Look little more in my HDL FAQ:

http://www.noveldv.com/verif/hdl_faq/FAQ00007.htm
http://www.noveldv.com/verif/hdl_faq/pr_dt.tar

This has one FLI example.

HTH
Ajeetha
www.noveldv.com
 
Thanks ..I am able run fli code using gcc compiler...

Here I have one more doubt.Here i am pasting sample results

D:\Modeltech_eval_6.1a\projectfolder\foreign>vsim -c test
Reading D:/Modeltech_eval_6.1a/tcl/vsim/pref.tcl

# 6.1a

# vsim -c test
# // ModelSim SE 6.1a Jul 19 2005
# //
# // Copyright Mentor Graphics Corporation 2005
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading D:\Modeltech_eval_6.1a\win32/../std.standard
# Loading D:\Modeltech_eval_6.1a\win32/../std.textio(body)
# Loading work.pkg(body)
# Loading test
# Loading work.test(only)
VSIM 1> run
# Integer = 0
# Enum = NOTE
# Real = 0
# String = abcde
VSIM 2>

after this line I have to exit the modelsim automatically....is there
any command avilable for exitting the modelsim by default?
I dont want to type exit to exit modelsim...


regds
priya
 
I recommend you read MTI manual/online help. Quickly, vsim -c <options>
-do "run.do" - in file run.do, add:

run;exit

HTH
Ajeetha
www.noveldv.com
 
Hi,

I am using fli code to send the input for and gate. and also
i want to send the vhdl AndGate output to fli code in the same
module..Here I am pasting my vhdl code


entity and4 is

port ( in1, in2 : in bit;
out1 : out bit
);
end;

architecture only of and4 is
attribute foreign : string;
attribute foreign of only : architecture "and_gate_init ./gates.sl";

begin
out1<=in1 and in2;
end;

-- -- --

entity testbench is
end testbench;

architecture a of testbench is

component and4
port ( in1, in2 : in bit;
out1 : out bit
);
end component;

signal bv1 : bit;
signal bv2 : bit;
signal bv3 : bit;

begin

t1 : and4
port map ( bv1, bv2, bv3 );

end a;


Here i am using single attribute for getting and gate value from fli
code...Its working fine..
here I have to send the output of andgate to fli code.

can we use two attribute in single module ?
if yes,
how to use two attribute in the same module.


regards,
priya..
 
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