how to represent "inout" data type in testbenches in "verilo

[linuxczar]

hi everybody
i didnt get how to represent "inout" datatype in testbenches in
verilog. i just tried with both "reg" and "wire" types but it didn't
worked.

thanks and regards
gkreddy.bh

 

[Alex]

On Mar 14, 11:43 am, "linuxczar" <h.264wo...@gmail.com> wrote:

hi everybody
i didnt get how to represent "inout" datatype in testbenches in
verilog. i just tried with both "reg" and "wire" types but it didn't
worked.

thanks and regards
gkreddy.bh

Here is an example :

wire [7:0] DQ;
reg [7:0] D = 0;
wire [7:0] Q;

assign DQ = (OE)? 8'bz : D;
assign Q = DQ;

dut dut (
....
.DQ (DQ), //inout
.OE (OE), //input
....
);

-Alex

 

[parag_paul@hotmail.com]

On Mar 14, 10:30 pm, "Alex" <agnu...@gmail.com> wrote:

On Mar 14, 11:43 am, "linuxczar" <h.264wo...@gmail.com> wrote:

hi everybody
i didnt get how to represent "inout" datatype in testbenches in
verilog. i just tried with both "reg" and "wire" types but it didn't
worked.

thanks and regards
gkreddy.bh

Here is an example :

wire [7:0] DQ;
reg [7:0] D = 0;
wire [7:0] Q;

assign DQ = (OE)? 8'bz : D;
assign Q = DQ;

dut dut (
....
.DQ (DQ), //inout
.OE (OE), //input
....
);

-Alex

Why cant we use the inout declaration directly

module top(a,b);
inout a,b;
endmodule


Alex

Did you mean that the simulator will use its own algorithm to coerce
the port to inout . DQ port