How to remove warnings?

K

Kumar

Guest
How to remove the warnings in the following vhdl program when we
compile it???
vsim>uvecC 010101010101010101
vsim>uveczero 00000000111111111
vsim>uvecone 00000000000000000


But gives waring while running??

Can anyone tell me the modficiaton in the program??


Please reply soon........



Program
========


entitiy shift is
port( C : in bit;
zero : in bit;
one : in bit;
output : out bit);
end shift;

architecture archi of shift is

constant S0 : bit_vector(4 downto 0) := "00001";
constant S1 : bit_vector(10 downto 0) := "00000010101";
constant S2 : bit_vector(5 downto 0) := "000101";
constant S3 : bit_vector(7 downto 0) := "00010011";

signal tmp1 : bit_vector(10 downto 0);
signal count : bit_vector(7 downto 0);
signal opcode : bit_vector(2 downto 0);

begin
count <= 0;
opcode <= 0;
process (C)

begin
if(count = 0) then
if(zero ='0' and one='0')then
tmp1 <= s0;
opcode <= 0;
end if;
if(zero ='0' and one='1')then
tmp1 <= s1;
opcode <= 1;
end if;
if(zero ='1' and one='0')then
tmp1 <= s2;
opcode <= 2;
end if;
if(zero ='1' and one='1')then
tmp1 <= s3;
opcode <= 3;
end if;



end if;

if(count < 4) then
if (C='1' and opcode = 0) then

output <= tmp1(0);

if(output = '1') then
count <= count + 1;
end if;

tmp1(0) <= tmp1(1);
tmp1(1) <= tmp1(2);
tmp1(2) <= tmp1(3);
tmp1(3) <= tmp1(4);
tmp1(4) <= output;
end if;

if (C='1' and opcode = 1) then

output <= tmp1(0);

if(output = '1') then
count <= count + 1;
end if;

tmp1(0) <= tmp1(1);
tmp1(1) <= tmp1(2);
tmp1(2) <= tmp1(3);
tmp1(3) <= tmp1(4);
tmp1(4) <= tmp1(5);
tmp1(5) <= tmp1(6);
tmp1(6) <= tmp1(7);
tmp1(7) <= tmp1(8);
tmp1(8) <= tmp1(9);
tmp1(9) <= tmp1(10);
tmp1(10) <= output;
end if;

if (C='1' and opcode = 2) then

output <= tmp1(0);

if(output = '1') then
count <= count + 1;
end if;

tmp1(0) <= tmp1(1);
tmp1(1) <= tmp1(2);
tmp1(2) <= tmp1(3);
tmp1(3) <= tmp1(4);
tmp1(4) <= tmp1(5);
tmp1(5) <= output;
end if;

if (C='1' and opcode = 3) then

output <= tmp1(0);

if(output = '1') then
count <= count + 1;
end if;

tmp1(0) <= tmp1(1);
tmp1(1) <= tmp1(2);
tmp1(2) <= tmp1(3);
tmp1(3) <= tmp1(4);
tmp1(4) <= tmp1(5);
tmp1(5) <= tmp1(6);
tmp1(6) <= tmp1(7);
tmp1(7) <= output;
end if;

else
count <= 0;
end if;

end process;
end archi;
 
Kumar,
Quite a few issues with your code - first of all, get a good VHDL
book. Read FAQ http://www.vhdl.org/comp.lang.vhdl

Attack first error and then go one at a time. TO start with:

count <= 0;

count --> bit vector, 0 --> Integer Try:

count <= (others => '0');

HTH
Ajeetha
--
www.noveldv.com
Interested in expert PSL/SVA training in Bangalore?
Visit www.noveldv.com/cvc.html
 
Didnt got what ur saying can u tell me in detail


or can u show me modified program!!!

Please reply me soon...

Kumar
 
Kumar,
Look at the first error from your compiler. I got error in
assignment:

count <= 0; -- Line 24?

That's what I elaborated in my last post.

Does that help? If not post your first error (that you get from your
compiler on your code). Unfortunately, not many in this forum will have
time & energy to "modify and send" the code back - they would rather
help you do it yourself.

Ajeetha
--
www.noveldv.com
Interested in expert PSL/SVA training in Bangalore?
Visit www.noveldv.com/cvc.html
 
Ok thanks Ajeetha!!!
But I was doing on my own and I stuck in between from where I cant
come out thats why I posted!! And I asked it as or "can u ..."


Ok fine Ajeetha
 
count and opcode have multiple drivers, i guess that is the warning you
are seeing. You have assigned "count <= 0" outside the process and you
modify it inside the process (clocked?)

Hope this helps
Sudhi
 
No it didnt worked!!!!!!!!
Please tell me the modification soon!!!

and
I replaced
count <= 0;
with
count --> bit vector, 0 --> Integer Try:

count <= (others => '0');

Still doesnt worked!!!

Ajeetha or sudhi please tell me soon!!!
 
Is C your clock?

Use the template for synchronous processes shown before in this forum:

Process(clock,reset) -- Only clock and reset, nothing else!
Begin
if reset='1' then
Reset all your signals here..
elsif rising_edge(clock) then
Do what has to be done..
end if;
-- Nothing more here!
End Process;


/Peter
 
On 9 Oct 2005 01:44:27 -0700, "Kumar" <kumarssss@gmail.com> wrote:

How to remove the warnings in the following vhdl program when we
compile it???
vsim>uvecC 010101010101010101
vsim>uveczero 00000000111111111
vsim>uvecone 00000000000000000


But gives waring while running??

Can anyone tell me the modficiaton in the program??


Please reply soon........



Program
========


entitiy shift is
port( C : in bit;
zero : in bit;
one : in bit;
output : out bit);
end shift;

architecture archi of shift is

constant S0 : bit_vector(4 downto 0) := "00001";
constant S1 : bit_vector(10 downto 0) := "00000010101";
constant S2 : bit_vector(5 downto 0) := "000101";
constant S3 : bit_vector(7 downto 0) := "00010011";

signal tmp1 : bit_vector(10 downto 0);
signal count : bit_vector(7 downto 0);
signal opcode : bit_vector(2 downto 0);

begin
count <= 0;
opcode <= 0;
process (C)

begin
if(count = 0) then
if(zero ='0' and one='0')then
tmp1 <= s0;
opcode <= 0;
end if;
if(zero ='0' and one='1')then
tmp1 <= s1;
opcode <= 1;
end if;
if(zero ='1' and one='0')then
tmp1 <= s2;
opcode <= 2;
end if;
if(zero ='1' and one='1')then
tmp1 <= s3;
opcode <= 3;
end if;

[snipped]
end process;
end archi;
Click to expand...
Kumar;

I see some of the same mistakes that I used to make. If you don't
have a book on VHDL, it would be wise to get one. Many people will
recommend Peter Ashenden's book "The Designer's Guide to VHDL". This
was the first book I bought, and was too much for me to handle at the
time (but it's a great reference book). Sundar Rajan's book
"Essential VHDL" was just what I was looking for. It has a lot of
examples, and shows logic diagrams that were generated from a VHDL
compiler.

your code:

1) Use the clocked process template that Peter showed. Also it would
be helpfull if you name your clock "clock" or "clk" (without the
quotes of course).

2) You are trying to assign a 0 to count and opcode. However, because
these are bit_vectors, you have to assign each bit. There are several
ways to do this:
opcode <= "000";
opcode <= (others => '0');

3) Both count and opcode are assigned values both outside of the
process and inside a process. This is wrong. Your VHDL compiler
should complain that they are "multi sourced". Moving the statements
above into the process will get rid of the error, but now you need to
add reset to your entity and process:

process( clock, reset )
begin
if (reset = '1') then
opcode <= (others => '0');
count <= (others => '0');
elsif rising_edge( clock ) then
...
end;
end process;


4) Because count is a bit_vector, it can't be compared against 0 or 4
or whatever. It would be simpler to change count to unsigned, and
then your comparisons would work:
signal count : unsigned(7 downto 0);

5) opcode <= 3; --won't work because opcode is a bit_vector.
Instead, do this:
opcode <= "011";

There are other problems, but I've given you enough hints for now.
Based on the number of errors in your code, you would be better off
starting with a simpler project.

-Dave Pollum
 
O really thanks!!

For clarifying my doubts in the program!!!
Well I have to code for my student regarding...
Design of memory controller for out of order memory
and

Implementation of any two branch predictors and its performance
evaluation


Where can I get the reference prorams for the same on the internet!!
 
On 13 Oct 2005 13:54:07 -0700, "Kumar" <kumarssss@gmail.com> wrote:

O really thanks!!

For clarifying my doubts in the program!!!
You're welcome.
Well I have to code for my student regarding...
Design of memory controller for out of order memory
and

Implementation of any two branch predictors and its performance
evaluation


Where can I get the reference prorams for the same on the internet!!
Perhaps using google and searching for "branch predictions" ??
Click to expand...
-Dave
 
I searched a lot but cant get really which willl be useful for me for
reference!!!''


Any other particular site??


Please tell
 
On 14 Oct 2005 06:34:11 -0700, "Kumar" <kumarssss@gmail.com> wrote:

I searched a lot but cant get really which willl be useful for me for
reference!!!''


Any other particular site??


Please tell
I know almost nothing about branch predictions except that I think
Click to expand...
they are used in high performance CPUs. I think that the Intel 89x86
CPUs would have them. Perhaps other CPUs such as ARM. I think that
pipelined CPUs do branch predecting, but I'm not 100% sure.

*********************************************************************
[1] I went to http://www.google.com, and asked for branch prediction:
These were on the first page.
*********************************************************************

Branch prediction in the Pentium family
How the branch prediction mechanism in the Pentium has been
uncovered with all ... The solution is branch prediction. The
microprocessor tries to predict ...
www.x86.org/articles/branch/branchprediction.htm - 26k - Oct 14, 2005
- Cached - Similar pages

Dynamic Branch Prediction
Clearly, the accuracy of a branch prediction scheme impacts CPU
performance. ... Note that since the branch prediction buffer is NOT a
cache, ...
www.csee.umbc.edu/~plusquel/611/slides/chap4_5.html - 29k - Cached -
Similar pages

Branch Prediction
Branch Prediction. Previous: Pipelining Next: Superscalar. In order to
make pipelining work efficiently, it is necessary to keep all the
stages full. ...
www.cs.fiu.edu/~downeyt/cop3402/prediction.html - 6k - Cached -
Similar pages

Evaluation of branch-prediction methods on traces from commercial ...
IBM Journal of Research and Development 43-4 - Digital multimedia
technology - Evaluation of branch-prediction methods on traces from
commercial ...
www.research.ibm.com/journal/rd/434/hilgendorf.html - 74k - Cached -
Similar pages

CBP_CFP
The 1st JILP Championship Branch Prediction Competition (CBP-1) ...
Championship Branch Prediction (CBP) is a branch predictor
competition. ...
www.jilp.org/cbp/ - 14k - Cached - Similar pages

2004 Championship Branch Prediction Workshop Agenda and Results
1:30 Idealized Piecewise Linear Branch Prediction, Daniel A.
Jiménez, ... 4:00 Branch Prediction Caveats and Second-Order Effects,
Phil Emma, IBM Research ...
www.jilp.org/cbp/Agenda-and-Results.htm - 15k - Cached - Similar
pages

branch prediction from FOLDOC
branch prediction. <processor, algorithm> A technique used in some
processors with instruction prefetch to guess whether a conditional
branch will be taken ...
foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?branch+prediction - 3k - Cached
- Similar pages

Branch Prediction Schemes
An alternative scheme is to predict the branch as taken. ... The
behavior of a predicted-taken cancelling branch depends on whether the
branch is taken or ...
www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/branchPred.html - 15k -
Cached - Similar pages

Accurate Static Branch Prediction by Value Range Propagation ...
The ability to predict at compile time the likelihood of a particular
branch being taken provides valuable information for several
optimizations, ...
citeseer.ist.psu.edu/patterson95accurate.html - 29k - Cached - Similar
pages

Branch Prediction For Free - Ball, Larus (ResearchIndex)
Many compilers rely on branch prediction to improve program
performance by identifying frequently executed regions and by aiding
in scheduling instructions.
citeseer.ist.psu.edu/ball93branch.html - 22k - Cached - Similar
pages

******************************************************************
[2] I searched in google's groups (http://groups.google.com), for
branch predictions. Here is the first page a results:
******************************************************************

pentium4 branch prediction and shanley's book
.... the paper "Demystifying Intel Branch Predictors"
http://www.ece.wisc.edu/~wddd/2002/
final/milenkovic.pdf I'm curious how the P4's branch prediction rate
stacks ...
comp.arch - Apr 5, 5:27 am by Daniel A. Jimenez - 5 messages - 4
authors

branch prediction, renaming, joins
.... That also depends on the branch prediction actually seeing the
same predictor
entries, which is not necessarily the case. But I ...
comp.arch - Dec 5 2003, 6:15 pm by Anton Ertl - 55 messages - 23
authors

ARM v5 branch prediction
Hi, This is regards the branch prediction in ARMv5 integer cores
(ARM10TDMI and
ARM10E). ... integer cores support more than one branch prediction at
a time. ...
comp.sys.arm - Nov 20 2003, 1:25 pm by Vijay - 4 messages - 3 authors

Branch prediction hints in an ISA
Does anyone know of any Instruction Sets that have an extra bit in the
branch
instruction to be used as a "hint" for the branch prediction logic?
.... ...
comp.compilers - Oct 12 2000, 10:03 pm by Daniel A. Jimenez - 12
messages - 12 authors

Branch prediction
I know that conditional jumps can confuse the x86 branch prediction,
but will a
loop statement do the same thing if ecx is not referenced at all in
the loop? ...
comp.lang.asm.x86 - Nov 22 2002, 1:55 pm by Stuart Dunn - 6 messages -
5 authors

Branch prediction question ...
It is correct insofar as indicating that there are two main places to
perform branch
prediction: at instruction fetch, or at instruction decode. ...
comp.arch - Dec 3 1998, 11:37 pm by Andy Glew - 7 messages - 5 authors

Branch prediction
.... I realise certain CPUs optimise their branch prediction units by
maintaining branch
prediction histories, which would help when a branch is encoun- tered
....
mailing.freebsd.hackers - Feb 17 2004, 6:21 am by David Schultz - 4
messages - 4 authors

Branch prediction (was: eliminating array bounds checking overhead ...
.... There are two sides to the branch prediction story: static
(compile-time)
prediction and dynamic prediction done by the prefetcher. ...
comp.compilers - May 4 2000, 12:01 pm by Patryk Zadarnowski - 27
messages - 22 authors

MPC860 Branch Prediction on Absolute Branches
.... branch bugs. The MPC860 User's guide (PDF version) has a table in
section
4.3.3.1 giving the static branch prediction. This says ...
comp.sys.powerpc.tech - Jul 6 2000, 7:27 pm by Richard Hendricks - 6
messages - 3 authors

Branch prediction in ARM8 (was Re: StrongARM in the Top TEN!)
.... free. I've just downloaded the ARM810 manual (while I wrote the
above)
and have read the section on branch prediction. It states ...
comp.sys.acorn.advocacy - Sep 27 1996, 3:23 pm by Torben AEgidius
Mogensen - 113 messages - 42 authors

I suspect that the comp.arch.* newgroups would be a good source of
info, or someone there may be able to point you to a place with better
information. Good Luck.

-Dave Pollum
 
Dave wrote:

Please tell
I know almost nothing about branch predictions except that I think
they are used in high performance CPUs. I think that the Intel 89x86
CPUs would have them. Perhaps other CPUs such as ARM. I think that
pipelined CPUs do branch predecting, but I'm not 100% sure.
Click to expand...
Look in the sourcecode/binaries for simplescalar. You can even enable
profiling using varying types of branch predictors to see how the fare
against each other for different programs.

-t
 
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