M
Mike
Guest
Hi,
I've made a schematic design with the Xilinx environment. When I load Xilinx
PACE (to assign pins, etc) I only see the pins in the list my top level had
in the past, not the updated situation
Anyone knows how to fix this (it's gotta be simple, I just can't seem to
find it) ?
Thanx!
Mike
I've made a schematic design with the Xilinx environment. When I load Xilinx
PACE (to assign pins, etc) I only see the pins in the list my top level had
in the past, not the updated situation
Anyone knows how to fix this (it's gotta be simple, I just can't seem to
find it) ?
Thanx!
Mike