how to reduce simulation time?

[sheri]

hi all,

how to reduce simulation time using modelsim.ini file.
I am using altera FPGA and wherein I am using lot of dprams which
takes more simulation time.Please help.

Thanks in advance.

 

[Kim Enkovaara]

sheri wrote:

how to reduce simulation time using modelsim.ini file.
I am using altera FPGA and wherein I am using lot of dprams which
takes more simulation time.Please help.

If that is RTL simulation just use inferred memories instead of
instantiated Altera blocks and the simulation will fly. And also
bear in mind that usually memory models made with shared variable
are faster and consume less memory than signal array based ones.

Also remove the PLL structures and put simple behavioral code
to their place. Altera PLL model is extremely slow to simulate.

If you have good enough Modelsim you can do profiling to find
the bottlenecks and places that are worth of optimizing for
simulation speed.

FPGA vendors seem to prefer really slow models for everything.
And I don't see any real reason to not infer memories unless
some fancy features are used (different width ports to memory etc.)
Usually ASIC vendors have much faster models fortunately.


--Kim