How to reduce jitter of 30-bit accumulator

[Am]

Hello,

I have a 30-bit accumulator in which I use the last bit as my clock out to
the design.

In the following way:



always @(posedge clk or negedge reset_n)

begin

if (!reset_n) nco_acc[29:0] <= 0;

else nco_acc[29:0] <= nco_acc[29:0] + constant;

end



assign clk_out = nco_acc[29];



I notice that when the constant is 26-bit width the jitter on the clk_out is
acceptable however when the constant is 27 bit wide the jitter on the
clk_out is not acceptable.

How can I reduce the amount of jitter on the clk_out.

(I can't use clkdll all are used already in the design)



Thank you,

 

[dbwalker0min@gmail.com]

The absolute magnitude of the jitter is constant at 1 clock. The
relative jitter of course increases as the increment to the nco
increases. The easiest way to improve the jitter would be to use a
faster clock and add a bit to the nco. If this is not an option,
perhaps you could use a latch to delay the clock an extra half cycle in
some cases (you have to work out what those cases are).

David Walker

Am wrote:

Hello,

I have a 30-bit accumulator in which I use the last bit as my clock out to
the design.

In the following way:



always @(posedge clk or negedge reset_n)

begin

if (!reset_n) nco_acc[29:0] <= 0;

else nco_acc[29:0] <= nco_acc[29:0] + constant;

end



assign clk_out = nco_acc[29];



I notice that when the constant is 26-bit width the jitter on the clk_out is
acceptable however when the constant is 27 bit wide the jitter on the
clk_out is not acceptable.

How can I reduce the amount of jitter on the clk_out.

(I can't use clkdll all are used already in the design)



Thank you,